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Consolidated single-slice SGPIO configuration functions into single sgpio_configure() function.

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This commit is contained in:
Jared Boone
2012-10-11 15:45:28 -07:00
parent 1b5574d2b9
commit 9b579232a7
5 changed files with 30 additions and 145 deletions
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156
firmware/common/sgpio.c
View File

@ -83,132 +83,10 @@ void sgpio_test_interface() {
}
}
void sgpio_configure_for_tx() {
// Disable all counters during configuration
SGPIO_CTRL_ENABLE = 0;
sgpio_configure_pin_functions();
// Set SGPIO output values.
SGPIO_GPIO_OUTREG =
(1L << 11) | // direction
(1L << 10); // disable
// Enable SGPIO pin outputs.
SGPIO_GPIO_OENREG =
(1L << 11) | // direction: TX: data to CPLD
(1L << 10) | // disable
(0L << 9) | // capture
(0L << 8) | // clock
0xFF; // data: output
SGPIO_OUT_MUX_CFG( 8) = 0; // SGPIO: Input: clock
SGPIO_OUT_MUX_CFG( 9) = 0; // SGPIO: Input: qualifier
SGPIO_OUT_MUX_CFG(10) = (0L << 4) | (4L << 0); // GPIO: Output: disable
SGPIO_OUT_MUX_CFG(11) = (0L << 4) | (4L << 0); // GPIO: Output: direction
for(uint_fast8_t i=0; i<8; i++) {
// SGPIO pin 0 outputs slice A bit "i".
SGPIO_OUT_MUX_CFG(i) =
(0L << 4) | // P_OE_CFG = 0
(9L << 0); // P_OUT_CFG = 9, dout_doutm8a (8-bit mode 8a)
}
// Slice A
SGPIO_MUX_CFG(SGPIO_SLICE_A) =
(0L << 12) | // CONCAT_ORDER = 0 (self-loop)
(1L << 11) | // CONCAT_ENABLE = 1 (concatenate data)
(0L << 9) | // QUALIFIER_SLICE_MODE = X
(1L << 7) | // QUALIFIER_PIN_MODE = 1 (SGPIO9)
(3L << 5) | // QUALIFIER_MODE = 3 (external SGPIO pin)
(0L << 3) | // CLK_SOURCE_SLICE_MODE = X
(0L << 1) | // CLK_SOURCE_PIN_MODE = 0 (SGPIO8)
(1L << 0); // EXT_CLK_ENABLE = 1, external clock signal (slice)
SGPIO_SLICE_MUX_CFG(SGPIO_SLICE_A) =
(0L << 8) | // INV_QUALIFIER = 0 (use normal qualifier)
(3L << 6) | // PARALLEL_MODE = 3 (shift 8 bits per clock)
(0L << 4) | // DATA_CAPTURE_MODE = 0 (detect rising edge)
(0L << 3) | // INV_OUT_CLK = 0 (normal clock)
(1L << 2) | // CLKGEN_MODE = 1 (use external pin clock)
(0L << 1) | // CLK_CAPTURE_MODE = 0 (use rising clock edge)
(0L << 0); // MATCH_MODE = 0 (do not match data)
SGPIO_PRESET(SGPIO_SLICE_A) = 0;
SGPIO_COUNT(SGPIO_SLICE_A) = 0;
SGPIO_POS(SGPIO_SLICE_A) = (0x3L << 8) | (0x3L << 0);
SGPIO_REG(SGPIO_SLICE_A) = 0x80808080; // Primary output data register
SGPIO_REG_SS(SGPIO_SLICE_A) = 0x80808080; // Shadow output data register
// Start SGPIO operation by enabling slice clocks.
SGPIO_CTRL_ENABLE =
(1L << SGPIO_SLICE_A)
;
}
void sgpio_configure_for_rx() {
// Disable all counters during configuration
SGPIO_CTRL_ENABLE = 0;
sgpio_configure_pin_functions();
// Set SGPIO output values.
SGPIO_GPIO_OUTREG =
(0L << 11) | // direction
(1L << 10); // disable
// Enable SGPIO pin outputs.
SGPIO_GPIO_OENREG =
(1L << 11) | // direction: RX: data from CPLD
(1L << 10) | // disable
(0L << 9) | // capture
(0L << 8) | // clock
0x00; // data: input
SGPIO_OUT_MUX_CFG( 8) = 0; // SGPIO: Input: clock
SGPIO_OUT_MUX_CFG( 9) = 0; // SGPIO: Input: qualifier
SGPIO_OUT_MUX_CFG(10) = (0L << 4) | (4L << 0); // GPIO: Output: disable
SGPIO_OUT_MUX_CFG(11) = (0L << 4) | (4L << 0); // GPIO: Output: direction
for(uint_fast8_t i=0; i<8; i++) {
SGPIO_OUT_MUX_CFG(i) =
(0L << 4) | // P_OE_CFG = 0
(9L << 0); // P_OUT_CFG = 9, dout_doutm8a (8-bit mode 8a)
}
// Slice A
SGPIO_MUX_CFG(SGPIO_SLICE_A) =
(0L << 12) | // CONCAT_ORDER = X
(0L << 11) | // CONCAT_ENABLE = 0 (concatenate data)
(0L << 9) | // QUALIFIER_SLICE_MODE = X
(1L << 7) | // QUALIFIER_PIN_MODE = 1 (SGPIO9)
(3L << 5) | // QUALIFIER_MODE = 3 (external SGPIO pin)
(0L << 3) | // CLK_SOURCE_SLICE_MODE = X
(0L << 1) | // CLK_SOURCE_PIN_MODE = 0 (SGPIO8)
(1L << 0); // EXT_CLK_ENABLE = 1, external clock signal (slice)
SGPIO_SLICE_MUX_CFG(SGPIO_SLICE_A) =
(0L << 8) | // INV_QUALIFIER = 0 (use normal qualifier)
(3L << 6) | // PARALLEL_MODE = 3 (shift 8 bits per clock)
(0L << 4) | // DATA_CAPTURE_MODE = 0 (detect rising edge)
(0L << 3) | // INV_OUT_CLK = X
(1L << 2) | // CLKGEN_MODE = 1 (use external pin clock)
(1L << 1) | // CLK_CAPTURE_MODE = 1 (use falling clock edge)
(0L << 0); // MATCH_MODE = 0 (do not match data)
SGPIO_PRESET(SGPIO_SLICE_A) = 0;
SGPIO_COUNT(SGPIO_SLICE_A) = 0;
SGPIO_POS(SGPIO_SLICE_A) = (0 << 8) | (0 << 0);
SGPIO_REG(SGPIO_SLICE_A) = 0xCAFEBABE; // Primary output data register
SGPIO_REG_SS(SGPIO_SLICE_A) = 0xDEADBEEF; // Shadow output data register
// Start SGPIO operation by enabling slice clocks.
SGPIO_CTRL_ENABLE =
(1L << SGPIO_SLICE_A)
;
}
void sgpio_configure_deep(const transceiver_mode_t transceiver_mode) {
void sgpio_configure(
const transceiver_mode_t transceiver_mode,
const bool multi_slice
) {
// Disable all counters during configuration
SGPIO_CTRL_ENABLE = 0;
@ -238,11 +116,13 @@ void sgpio_configure_deep(const transceiver_mode_t transceiver_mode) {
SGPIO_OUT_MUX_CFG(10) = (0L << 4) | (4L << 0); // GPIO: Output: disable
SGPIO_OUT_MUX_CFG(11) = (0L << 4) | (4L << 0); // GPIO: Output: direction
const uint_fast8_t output_multiplexing_mode =
multi_slice ? 11 : 9;
for(uint_fast8_t i=0; i<8; i++) {
// SGPIO pin 0 outputs slice A bit "i".
SGPIO_OUT_MUX_CFG(i) =
(0L << 4) | // P_OE_CFG = 0
(11L << 0); // P_OUT_CFG = 11, dout_doutm8c (8-bit mode 8c)
(output_multiplexing_mode << 0);
}
const uint_fast8_t slice_indices[] = {
@ -256,15 +136,19 @@ void sgpio_configure_deep(const transceiver_mode_t transceiver_mode) {
SGPIO_SLICE_L,
};
const bool single_slice = !multi_slice;
const uint_fast8_t slice_count = multi_slice ? 8 : 1;
uint32_t slice_enable_mask = 0;
for(uint_fast8_t i=0; i<8; i++) {
uint_fast8_t slice_index = slice_indices[i];
for(uint_fast8_t i=0; i<slice_count; i++) {
const uint_fast8_t slice_index = slice_indices[i];
const bool input_slice = (i == 0) && (transceiver_mode == TRANSCEIVER_MODE_RX);
const uint_fast8_t concat_order = input_slice ? 0 : 3;
const uint_fast8_t concat_enable = input_slice ? 0 : 1;
const uint_fast8_t concat_order = (input_slice || single_slice) ? 0 : 3;
const uint_fast8_t concat_enable = (input_slice || single_slice) ? 0 : 1;
const uint_fast8_t pos = multi_slice ? 0x1f : 0x03;
SGPIO_MUX_CFG(slice_index) =
(concat_order << 12) | // CONCAT_ORDER = 3 (eight slices)
(concat_enable << 11) | // CONCAT_ENABLE = 1 (concatenate data)
(concat_order << 12) |
(concat_enable << 11) |
(0L << 9) | // QUALIFIER_SLICE_MODE = X
(1L << 7) | // QUALIFIER_PIN_MODE = 1 (SGPIO9)
(3L << 5) | // QUALIFIER_MODE = 3 (external SGPIO pin)
@ -283,9 +167,9 @@ void sgpio_configure_deep(const transceiver_mode_t transceiver_mode) {
SGPIO_PRESET(slice_index) = 0; // External clock, don't care
SGPIO_COUNT(slice_index) = 0; // External clock, don't care
SGPIO_POS(slice_index) = (0x1f << 8) | (0x1f << 0);
SGPIO_REG(slice_index) = 0xFFFFFFFF; // Primary output data register
SGPIO_REG_SS(slice_index) = 0xFFFFFFFF; // Shadow output data register
SGPIO_POS(slice_index) = (pos << 8) | (pos << 0);
SGPIO_REG(slice_index) = 0x80808080; // Primary output data register
SGPIO_REG_SS(slice_index) = 0x80808080; // Shadow output data register
slice_enable_mask |= (1 << slice_index);
}

7
firmware/common/sgpio.h
View File

@ -26,9 +26,10 @@
void sgpio_configure_pin_functions();
void sgpio_test_interface();
void sgpio_configure_for_tx();
void sgpio_configure_for_rx();
void sgpio_configure_deep(const transceiver_mode_t transceiver_mode);
void sgpio_configure(
const transceiver_mode_t transceiver_mode,
const bool multi_slice
);
void sgpio_cpld_stream_enable();
void sgpio_cpld_stream_disable();
bool sgpio_cpld_stream_is_enabled();

4
firmware/sgpio-rx/sgpio-rx.c
View File

@ -33,7 +33,7 @@
#include <sgpio.h>
void tx_test() {
sgpio_configure_for_tx();
sgpio_configure(TRANSCEIVER_MODE_TX, false);
// LSB goes out first, samples are 0x<Q1><I1><Q0><I0>
volatile uint32_t buffer[] = {
@ -54,7 +54,7 @@ void tx_test() {
}
void rx_test() {
sgpio_configure_for_rx();
sgpio_configure(TRANSCEIVER_MODE_RX, false);
volatile uint32_t buffer[4096];
uint32_t i = 0;

4
firmware/sgpio/sgpio.c
View File

@ -31,7 +31,7 @@
#include <sgpio.h>
void tx_test() {
sgpio_configure_for_tx();
sgpio_configure(TRANSCEIVER_MODE_TX, false);
// LSB goes out first, samples are 0x<Q1><I1><Q0><I0>
volatile uint32_t buffer[] = {
@ -52,7 +52,7 @@ void tx_test() {
}
void rx_test() {
sgpio_configure_for_rx();
sgpio_configure(TRANSCEIVER_MODE_RX, false);
volatile uint32_t buffer[4096];
uint32_t i = 0;

4
firmware/usb_performance/usb_performance.c
View File

@ -205,10 +205,10 @@ bool usb_set_configuration(
// library.
if( device->configuration && (device->configuration->number == 1) ) {
if( transceiver_mode == TRANSCEIVER_MODE_RX ) {
sgpio_configure_deep(transceiver_mode);
sgpio_configure(transceiver_mode, true);
usb_endpoint_init(&usb_endpoint_bulk_in);
} else {
sgpio_configure_deep(transceiver_mode);
sgpio_configure(transceiver_mode, true);
usb_endpoint_init(&usb_endpoint_bulk_out);
}