From 9b579232a72f9b47ed507b5679c6e0bf5fdb160b Mon Sep 17 00:00:00 2001 From: Jared Boone Date: Thu, 11 Oct 2012 15:45:28 -0700 Subject: [PATCH] Consolidated single-slice SGPIO configuration functions into single sgpio_configure() function. --- firmware/common/sgpio.c | 156 +++------------------ firmware/common/sgpio.h | 7 +- firmware/sgpio-rx/sgpio-rx.c | 4 +- firmware/sgpio/sgpio.c | 4 +- firmware/usb_performance/usb_performance.c | 4 +- 5 files changed, 30 insertions(+), 145 deletions(-) diff --git a/firmware/common/sgpio.c b/firmware/common/sgpio.c index d81a5ac2..c04f39da 100644 --- a/firmware/common/sgpio.c +++ b/firmware/common/sgpio.c @@ -83,132 +83,10 @@ void sgpio_test_interface() { } } -void sgpio_configure_for_tx() { - // Disable all counters during configuration - SGPIO_CTRL_ENABLE = 0; - - sgpio_configure_pin_functions(); - - // Set SGPIO output values. - SGPIO_GPIO_OUTREG = - (1L << 11) | // direction - (1L << 10); // disable - - // Enable SGPIO pin outputs. - SGPIO_GPIO_OENREG = - (1L << 11) | // direction: TX: data to CPLD - (1L << 10) | // disable - (0L << 9) | // capture - (0L << 8) | // clock - 0xFF; // data: output - - SGPIO_OUT_MUX_CFG( 8) = 0; // SGPIO: Input: clock - SGPIO_OUT_MUX_CFG( 9) = 0; // SGPIO: Input: qualifier - SGPIO_OUT_MUX_CFG(10) = (0L << 4) | (4L << 0); // GPIO: Output: disable - SGPIO_OUT_MUX_CFG(11) = (0L << 4) | (4L << 0); // GPIO: Output: direction - - for(uint_fast8_t i=0; i<8; i++) { - // SGPIO pin 0 outputs slice A bit "i". - SGPIO_OUT_MUX_CFG(i) = - (0L << 4) | // P_OE_CFG = 0 - (9L << 0); // P_OUT_CFG = 9, dout_doutm8a (8-bit mode 8a) - } - - // Slice A - SGPIO_MUX_CFG(SGPIO_SLICE_A) = - (0L << 12) | // CONCAT_ORDER = 0 (self-loop) - (1L << 11) | // CONCAT_ENABLE = 1 (concatenate data) - (0L << 9) | // QUALIFIER_SLICE_MODE = X - (1L << 7) | // QUALIFIER_PIN_MODE = 1 (SGPIO9) - (3L << 5) | // QUALIFIER_MODE = 3 (external SGPIO pin) - (0L << 3) | // CLK_SOURCE_SLICE_MODE = X - (0L << 1) | // CLK_SOURCE_PIN_MODE = 0 (SGPIO8) - (1L << 0); // EXT_CLK_ENABLE = 1, external clock signal (slice) - - SGPIO_SLICE_MUX_CFG(SGPIO_SLICE_A) = - (0L << 8) | // INV_QUALIFIER = 0 (use normal qualifier) - (3L << 6) | // PARALLEL_MODE = 3 (shift 8 bits per clock) - (0L << 4) | // DATA_CAPTURE_MODE = 0 (detect rising edge) - (0L << 3) | // INV_OUT_CLK = 0 (normal clock) - (1L << 2) | // CLKGEN_MODE = 1 (use external pin clock) - (0L << 1) | // CLK_CAPTURE_MODE = 0 (use rising clock edge) - (0L << 0); // MATCH_MODE = 0 (do not match data) - - SGPIO_PRESET(SGPIO_SLICE_A) = 0; - SGPIO_COUNT(SGPIO_SLICE_A) = 0; - SGPIO_POS(SGPIO_SLICE_A) = (0x3L << 8) | (0x3L << 0); - SGPIO_REG(SGPIO_SLICE_A) = 0x80808080; // Primary output data register - SGPIO_REG_SS(SGPIO_SLICE_A) = 0x80808080; // Shadow output data register - - // Start SGPIO operation by enabling slice clocks. - SGPIO_CTRL_ENABLE = - (1L << SGPIO_SLICE_A) - ; -} - -void sgpio_configure_for_rx() { - // Disable all counters during configuration - SGPIO_CTRL_ENABLE = 0; - - sgpio_configure_pin_functions(); - - // Set SGPIO output values. - SGPIO_GPIO_OUTREG = - (0L << 11) | // direction - (1L << 10); // disable - - // Enable SGPIO pin outputs. - SGPIO_GPIO_OENREG = - (1L << 11) | // direction: RX: data from CPLD - (1L << 10) | // disable - (0L << 9) | // capture - (0L << 8) | // clock - 0x00; // data: input - - SGPIO_OUT_MUX_CFG( 8) = 0; // SGPIO: Input: clock - SGPIO_OUT_MUX_CFG( 9) = 0; // SGPIO: Input: qualifier - SGPIO_OUT_MUX_CFG(10) = (0L << 4) | (4L << 0); // GPIO: Output: disable - SGPIO_OUT_MUX_CFG(11) = (0L << 4) | (4L << 0); // GPIO: Output: direction - - for(uint_fast8_t i=0; i<8; i++) { - SGPIO_OUT_MUX_CFG(i) = - (0L << 4) | // P_OE_CFG = 0 - (9L << 0); // P_OUT_CFG = 9, dout_doutm8a (8-bit mode 8a) - } - - // Slice A - SGPIO_MUX_CFG(SGPIO_SLICE_A) = - (0L << 12) | // CONCAT_ORDER = X - (0L << 11) | // CONCAT_ENABLE = 0 (concatenate data) - (0L << 9) | // QUALIFIER_SLICE_MODE = X - (1L << 7) | // QUALIFIER_PIN_MODE = 1 (SGPIO9) - (3L << 5) | // QUALIFIER_MODE = 3 (external SGPIO pin) - (0L << 3) | // CLK_SOURCE_SLICE_MODE = X - (0L << 1) | // CLK_SOURCE_PIN_MODE = 0 (SGPIO8) - (1L << 0); // EXT_CLK_ENABLE = 1, external clock signal (slice) - - SGPIO_SLICE_MUX_CFG(SGPIO_SLICE_A) = - (0L << 8) | // INV_QUALIFIER = 0 (use normal qualifier) - (3L << 6) | // PARALLEL_MODE = 3 (shift 8 bits per clock) - (0L << 4) | // DATA_CAPTURE_MODE = 0 (detect rising edge) - (0L << 3) | // INV_OUT_CLK = X - (1L << 2) | // CLKGEN_MODE = 1 (use external pin clock) - (1L << 1) | // CLK_CAPTURE_MODE = 1 (use falling clock edge) - (0L << 0); // MATCH_MODE = 0 (do not match data) - - SGPIO_PRESET(SGPIO_SLICE_A) = 0; - SGPIO_COUNT(SGPIO_SLICE_A) = 0; - SGPIO_POS(SGPIO_SLICE_A) = (0 << 8) | (0 << 0); - SGPIO_REG(SGPIO_SLICE_A) = 0xCAFEBABE; // Primary output data register - SGPIO_REG_SS(SGPIO_SLICE_A) = 0xDEADBEEF; // Shadow output data register - - // Start SGPIO operation by enabling slice clocks. - SGPIO_CTRL_ENABLE = - (1L << SGPIO_SLICE_A) - ; -} - -void sgpio_configure_deep(const transceiver_mode_t transceiver_mode) { +void sgpio_configure( + const transceiver_mode_t transceiver_mode, + const bool multi_slice +) { // Disable all counters during configuration SGPIO_CTRL_ENABLE = 0; @@ -238,11 +116,13 @@ void sgpio_configure_deep(const transceiver_mode_t transceiver_mode) { SGPIO_OUT_MUX_CFG(10) = (0L << 4) | (4L << 0); // GPIO: Output: disable SGPIO_OUT_MUX_CFG(11) = (0L << 4) | (4L << 0); // GPIO: Output: direction + const uint_fast8_t output_multiplexing_mode = + multi_slice ? 11 : 9; for(uint_fast8_t i=0; i<8; i++) { // SGPIO pin 0 outputs slice A bit "i". SGPIO_OUT_MUX_CFG(i) = (0L << 4) | // P_OE_CFG = 0 - (11L << 0); // P_OUT_CFG = 11, dout_doutm8c (8-bit mode 8c) + (output_multiplexing_mode << 0); } const uint_fast8_t slice_indices[] = { @@ -256,15 +136,19 @@ void sgpio_configure_deep(const transceiver_mode_t transceiver_mode) { SGPIO_SLICE_L, }; + const bool single_slice = !multi_slice; + const uint_fast8_t slice_count = multi_slice ? 8 : 1; + uint32_t slice_enable_mask = 0; - for(uint_fast8_t i=0; i<8; i++) { - uint_fast8_t slice_index = slice_indices[i]; + for(uint_fast8_t i=0; i void tx_test() { - sgpio_configure_for_tx(); + sgpio_configure(TRANSCEIVER_MODE_TX, false); // LSB goes out first, samples are 0x volatile uint32_t buffer[] = { @@ -54,7 +54,7 @@ void tx_test() { } void rx_test() { - sgpio_configure_for_rx(); + sgpio_configure(TRANSCEIVER_MODE_RX, false); volatile uint32_t buffer[4096]; uint32_t i = 0; diff --git a/firmware/sgpio/sgpio.c b/firmware/sgpio/sgpio.c index 88008313..fbf40ffd 100644 --- a/firmware/sgpio/sgpio.c +++ b/firmware/sgpio/sgpio.c @@ -31,7 +31,7 @@ #include void tx_test() { - sgpio_configure_for_tx(); + sgpio_configure(TRANSCEIVER_MODE_TX, false); // LSB goes out first, samples are 0x volatile uint32_t buffer[] = { @@ -52,7 +52,7 @@ void tx_test() { } void rx_test() { - sgpio_configure_for_rx(); + sgpio_configure(TRANSCEIVER_MODE_RX, false); volatile uint32_t buffer[4096]; uint32_t i = 0; diff --git a/firmware/usb_performance/usb_performance.c b/firmware/usb_performance/usb_performance.c index 1a54927a..2766981d 100644 --- a/firmware/usb_performance/usb_performance.c +++ b/firmware/usb_performance/usb_performance.c @@ -205,10 +205,10 @@ bool usb_set_configuration( // library. if( device->configuration && (device->configuration->number == 1) ) { if( transceiver_mode == TRANSCEIVER_MODE_RX ) { - sgpio_configure_deep(transceiver_mode); + sgpio_configure(transceiver_mode, true); usb_endpoint_init(&usb_endpoint_bulk_in); } else { - sgpio_configure_deep(transceiver_mode); + sgpio_configure(transceiver_mode, true); usb_endpoint_init(&usb_endpoint_bulk_out); }