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Configure APB3 for appropriate clock sources during start-up.

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This commit is contained in:
Jared Boone
2014-06-15 10:10:53 -07:00
parent 44df9d1f82
commit 9b435f3b7e
1 changed files with 11 additions and 0 deletions
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11
firmware/common/hackrf_core.c
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@ -261,6 +261,9 @@ void cpu_clock_init(void)
/* use IRC as clock source for APB1 (including I2C0) */ /* use IRC as clock source for APB1 (including I2C0) */
CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_IRC); CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_IRC);
/* use IRC as clock source for APB3 */
CGU_BASE_APB3_CLK = CGU_BASE_APB3_CLK_CLK_SEL(CGU_SRC_IRC);
i2c0_init(15); i2c0_init(15);
si5351c_disable_all_outputs(); si5351c_disable_all_outputs();
@ -365,6 +368,10 @@ void cpu_clock_init(void)
CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_AUTOBLOCK(1) CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_AUTOBLOCK(1)
| CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_XTAL); | CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_XTAL);
/* use XTAL_OSC as clock source for APB3 */
CGU_BASE_APB3_CLK = CGU_BASE_APB3_CLK_AUTOBLOCK(1)
| CGU_BASE_APB3_CLK_CLK_SEL(CGU_SRC_XTAL);
cpu_clock_pll1_low_speed(); cpu_clock_pll1_low_speed();
/* use PLL1 as clock source for BASE_M4_CLK (CPU) */ /* use PLL1 as clock source for BASE_M4_CLK (CPU) */
@ -400,6 +407,10 @@ void cpu_clock_init(void)
/* Switch APB1 clock over to use PLL1 (204MHz) */ /* Switch APB1 clock over to use PLL1 (204MHz) */
CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_AUTOBLOCK(1) CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_AUTOBLOCK(1)
| CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_PLL1); | CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_PLL1);
/* Switch APB3 clock over to use PLL1 (204MHz) */
CGU_BASE_APB3_CLK = CGU_BASE_APB3_CLK_AUTOBLOCK(1)
| CGU_BASE_APB3_CLK_CLK_SEL(CGU_SRC_PLL1);
} }