From 9b435f3b7e8b224edd4340686313fc11adf83e78 Mon Sep 17 00:00:00 2001 From: Jared Boone Date: Sun, 15 Jun 2014 10:10:53 -0700 Subject: [PATCH] Configure APB3 for appropriate clock sources during start-up. --- firmware/common/hackrf_core.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/firmware/common/hackrf_core.c b/firmware/common/hackrf_core.c index dc4c4708..c06452d4 100644 --- a/firmware/common/hackrf_core.c +++ b/firmware/common/hackrf_core.c @@ -261,6 +261,9 @@ void cpu_clock_init(void) /* use IRC as clock source for APB1 (including I2C0) */ CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_IRC); + /* use IRC as clock source for APB3 */ + CGU_BASE_APB3_CLK = CGU_BASE_APB3_CLK_CLK_SEL(CGU_SRC_IRC); + i2c0_init(15); si5351c_disable_all_outputs(); @@ -365,6 +368,10 @@ void cpu_clock_init(void) CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_AUTOBLOCK(1) | CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_XTAL); + /* use XTAL_OSC as clock source for APB3 */ + CGU_BASE_APB3_CLK = CGU_BASE_APB3_CLK_AUTOBLOCK(1) + | CGU_BASE_APB3_CLK_CLK_SEL(CGU_SRC_XTAL); + cpu_clock_pll1_low_speed(); /* use PLL1 as clock source for BASE_M4_CLK (CPU) */ @@ -400,6 +407,10 @@ void cpu_clock_init(void) /* Switch APB1 clock over to use PLL1 (204MHz) */ CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_AUTOBLOCK(1) | CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_PLL1); + + /* Switch APB3 clock over to use PLL1 (204MHz) */ + CGU_BASE_APB3_CLK = CGU_BASE_APB3_CLK_AUTOBLOCK(1) + | CGU_BASE_APB3_CLK_CLK_SEL(CGU_SRC_PLL1); }