Added link to Dangerous Prototypes information on how to switch buffers in Bus Blaster v2.

This commit is contained in:
Jared Boone
2012-07-19 16:50:58 -07:00
parent 6121294550
commit 892f4c1eea

View File

@ -11,7 +11,7 @@ To build this VHDL project and produce an SVF file for flashing the CPLD:
To program the SVF file into the CPLD: To program the SVF file into the CPLD:
* Dangerous Prototypes Bus Blaster v2: * Dangerous Prototypes Bus Blaster v2:
* Configured with JTAGKey buffers. * Configured with [JTAGKey buffers](http://dangerousprototypes.com/docs/Bus_Blaster_v2_buffer_logic).
* Connected to CPLD JTAG signals on Jellybean. * Connected to CPLD JTAG signals on Jellybean.
* urJTAG built with libftdi support. * urJTAG built with libftdi support.