Merge pull request #1106 from martinling/pll-startup
Implement NXP's recommended setup sequence for the PLL and M4 clock
This commit is contained in:
@ -46,7 +46,6 @@
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#include "gpio_lpc.h"
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#define WAIT_CPU_CLOCK_INIT_DELAY (10000)
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/* GPIO Output PinMux */
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static struct gpio_t gpio_led[] = {
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GPIO(2, 1),
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@ -299,6 +298,19 @@ void delay(uint32_t duration)
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__asm__("nop");
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}
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void delay_us_at_mhz(uint32_t us, uint32_t mhz)
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{
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// The loop below takes 4 cycles per iteration.
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uint32_t loop_iterations = (us * mhz) / 4;
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asm volatile (
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"start%=:\n"
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" subs %[ITERATIONS], #1\n" // 1 cycle
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" bpl start%=\n" // 3 cycles
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:
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: [ITERATIONS] "r" (loop_iterations)
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);
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}
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/* GCD algo from wikipedia */
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/* http://en.wikipedia.org/wiki/Greatest_common_divisor */
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static uint32_t
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@ -485,54 +497,65 @@ This function shall be called after cpu_clock_init().
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*/
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static void cpu_clock_pll1_max_speed(void)
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{
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uint32_t pll_reg;
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uint32_t reg_val;
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/* Configure PLL1 to Intermediate Clock (between 90 MHz and 110 MHz) */
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/* Integer mode:
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FCLKOUT = M*(FCLKIN/N)
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FCCO = 2*P*FCLKOUT = 2*P*M*(FCLKIN/N)
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*/
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pll_reg = CGU_PLL1_CTRL;
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/* Clear PLL1 bits */
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pll_reg &= ~( CGU_PLL1_CTRL_CLK_SEL_MASK | CGU_PLL1_CTRL_PD_MASK | CGU_PLL1_CTRL_FBSEL_MASK | /* CLK SEL, PowerDown , FBSEL */
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CGU_PLL1_CTRL_BYPASS_MASK | /* BYPASS */
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CGU_PLL1_CTRL_DIRECT_MASK | /* DIRECT */
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CGU_PLL1_CTRL_PSEL_MASK | CGU_PLL1_CTRL_MSEL_MASK | CGU_PLL1_CTRL_NSEL_MASK ); /* PSEL, MSEL, NSEL- divider ratios */
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/* Set PLL1 up to 12MHz * 8 = 96MHz. */
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pll_reg |= CGU_PLL1_CTRL_CLK_SEL(CGU_SRC_XTAL)
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| CGU_PLL1_CTRL_PSEL(0)
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| CGU_PLL1_CTRL_NSEL(0)
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| CGU_PLL1_CTRL_MSEL(7)
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| CGU_PLL1_CTRL_FBSEL(1);
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CGU_PLL1_CTRL = pll_reg;
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/* wait until stable */
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/* This function implements the sequence recommended in:
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* UM10503 Rev 2.4 (Aug 2018), section 13.2.1.1, page 167. */
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/* 1. Select the IRC as BASE_M4_CLK source. */
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reg_val = CGU_BASE_M4_CLK;
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reg_val &= ~CGU_BASE_M4_CLK_CLK_SEL_MASK;
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reg_val |= CGU_BASE_M4_CLK_CLK_SEL(CGU_SRC_IRC) |
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CGU_BASE_M4_CLK_AUTOBLOCK(1);
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CGU_BASE_M4_CLK = reg_val;
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/* 2. Enable the crystal oscillator. */
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CGU_XTAL_OSC_CTRL &= ~CGU_XTAL_OSC_CTRL_ENABLE_MASK;
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/* 3. Wait 250us. */
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delay_us_at_mhz(250, 12);
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/* 4. Set the AUTOBLOCK bit. */
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CGU_PLL1_CTRL |= CGU_PLL1_CTRL_AUTOBLOCK(1);
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/* 5. Reconfigure PLL1 to produce the final output frequency, with the
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* crystal oscillator as clock source. */
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reg_val = CGU_PLL1_CTRL;
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reg_val &= ~( CGU_PLL1_CTRL_CLK_SEL_MASK |
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CGU_PLL1_CTRL_PD_MASK |
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CGU_PLL1_CTRL_FBSEL_MASK |
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CGU_PLL1_CTRL_BYPASS_MASK |
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CGU_PLL1_CTRL_DIRECT_MASK |
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CGU_PLL1_CTRL_PSEL_MASK |
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CGU_PLL1_CTRL_MSEL_MASK |
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CGU_PLL1_CTRL_NSEL_MASK );
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/* Set PLL1 up to 12MHz * 17 = 204MHz.
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* Direct mode: FCLKOUT = FCCO = M*(FCLKIN/N) */
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reg_val |= CGU_PLL1_CTRL_CLK_SEL(CGU_SRC_XTAL) |
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CGU_PLL1_CTRL_PSEL(0) |
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CGU_PLL1_CTRL_NSEL(0) |
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CGU_PLL1_CTRL_MSEL(16) |
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CGU_PLL1_CTRL_FBSEL(0) |
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CGU_PLL1_CTRL_DIRECT(1);
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CGU_PLL1_CTRL = reg_val;
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/* 6. Wait for PLL1 to lock. */
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while (!(CGU_PLL1_STAT & CGU_PLL1_STAT_LOCK_MASK));
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/* use PLL1 as clock source for BASE_M4_CLK (CPU) */
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CGU_BASE_M4_CLK = (CGU_BASE_M4_CLK_CLK_SEL(CGU_SRC_PLL1) | CGU_BASE_M4_CLK_AUTOBLOCK(1));
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/* 7. Set the PLL1 P-divider to divide by 2 (DIRECT=0, PSEL=0). */
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CGU_PLL1_CTRL &= ~CGU_PLL1_CTRL_DIRECT_MASK;
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/* Wait before to switch to max speed */
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delay(WAIT_CPU_CLOCK_INIT_DELAY);
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/* 8. Select PLL1 as BASE_M4_CLK source. */
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reg_val = CGU_BASE_M4_CLK;
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reg_val &= ~CGU_BASE_M4_CLK_CLK_SEL_MASK;
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reg_val |= CGU_BASE_M4_CLK_CLK_SEL(CGU_SRC_PLL1);
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CGU_BASE_M4_CLK = reg_val;
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/* Configure PLL1 Max Speed */
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/* Direct mode: FCLKOUT = FCCO = M*(FCLKIN/N) */
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pll_reg = CGU_PLL1_CTRL;
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/* Clear PLL1 bits */
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pll_reg &= ~( CGU_PLL1_CTRL_CLK_SEL_MASK | CGU_PLL1_CTRL_PD_MASK | CGU_PLL1_CTRL_FBSEL_MASK | /* CLK SEL, PowerDown , FBSEL */
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CGU_PLL1_CTRL_BYPASS_MASK | /* BYPASS */
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CGU_PLL1_CTRL_DIRECT_MASK | /* DIRECT */
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CGU_PLL1_CTRL_PSEL_MASK | CGU_PLL1_CTRL_MSEL_MASK | CGU_PLL1_CTRL_NSEL_MASK ); /* PSEL, MSEL, NSEL- divider ratios */
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/* Set PLL1 up to 12MHz * 17 = 204MHz. */
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pll_reg |= CGU_PLL1_CTRL_CLK_SEL(CGU_SRC_XTAL)
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| CGU_PLL1_CTRL_PSEL(0)
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| CGU_PLL1_CTRL_NSEL(0)
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| CGU_PLL1_CTRL_MSEL(16)
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| CGU_PLL1_CTRL_FBSEL(1)
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| CGU_PLL1_CTRL_DIRECT(1);
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CGU_PLL1_CTRL = pll_reg;
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/* wait until stable */
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while (!(CGU_PLL1_STAT & CGU_PLL1_STAT_LOCK_MASK));
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/* 9. Wait 50us. */
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delay_us_at_mhz(50, 104);
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/* 10. Set the PLL1 P-divider to direct output mode (DIRECT=1). */
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CGU_PLL1_CTRL |= CGU_PLL1_CTRL_DIRECT_MASK;
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}
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/* clock startup for LPC4320 configure PLL1 to max speed (204MHz).
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@ -598,14 +621,7 @@ void cpu_clock_init(void)
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/* set xtal oscillator to low frequency mode */
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CGU_XTAL_OSC_CTRL &= ~CGU_XTAL_OSC_CTRL_HF_MASK;
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/* power on the oscillator and wait until stable */
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CGU_XTAL_OSC_CTRL &= ~CGU_XTAL_OSC_CTRL_ENABLE_MASK;
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/* Wait about 100us after Crystal Power ON */
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delay(WAIT_CPU_CLOCK_INIT_DELAY);
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/* use XTAL_OSC as clock source for BASE_M4_CLK (CPU) */
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CGU_BASE_M4_CLK = (CGU_BASE_M4_CLK_CLK_SEL(CGU_SRC_XTAL) | CGU_BASE_M4_CLK_AUTOBLOCK(1));
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cpu_clock_pll1_max_speed();
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/* use XTAL_OSC as clock source for APB1 */
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CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_AUTOBLOCK(1)
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@ -615,8 +631,6 @@ void cpu_clock_init(void)
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CGU_BASE_APB3_CLK = CGU_BASE_APB3_CLK_AUTOBLOCK(1)
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| CGU_BASE_APB3_CLK_CLK_SEL(CGU_SRC_XTAL);
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cpu_clock_pll1_max_speed();
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/* use XTAL_OSC as clock source for PLL0USB */
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CGU_PLL0USB_CTRL = CGU_PLL0USB_CTRL_PD(1)
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| CGU_PLL0USB_CTRL_AUTOBLOCK(1)
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