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docs: Remove outdated clocking page

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Michael Ossmann
2022-09-21 04:09:54 -04:00
parent e623c7aed7
commit 5c812681ab
2 changed files with 0 additions and 39 deletions
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38
docs/source/clocking.rst
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@ -1,38 +0,0 @@
================================================
Clocking Signals
================================================
HackRF clock signals are generated by the Si5351. The plan so far:
* crystal frequency: 25 MHz (supports 25 or 27 MHz)
* optional clock input frequency: 10 MHz recommended (supports 10 to 40 MHz, or higher with division)
* VCO frequency: 800 MHz (supports 600 to 900 MHz)
* MAX2837 clock: 40 MHz
* preferred MAX5864 clocks: 8, 10, 12.5, 16, 20 MHz
* A clock at double the MAX5864 rate will be delivered to the CPLD and SGPIO.
* LPC43xx clock: 12 MHz (from separate crystal so the ROM-based USB DFU will work)
Lemondrop+Jellybean Si5351 output mapping:
* CLK0 -> MAX2837
* CLK1 -> MAX5864/CPLD
* CLK2 -> CPLD
* CLK3 -> CPLD
* CLK4 -> LPC4330
* CLK5 -> RFFC5072
* CLK6 -> extra
* CLK7 -> extra
Jawbreaker output mapping:
* CLK0 -> MAX5864/CPLD
* CLK1 -> CPLD
* CLK2 -> SGPIO
* CLK3 -> external clock output
* CLK4 -> RFFC5072
* CLK5 -> MAX2837
* CLK6 -> none
* CLK7 -> LPC4330 (but LPC4330 will start up on its own crystal)

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docs/source/index.rst
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@ -42,7 +42,6 @@ Welcome to HackRF's documentation!
enclosure_options
hackrfs_buttons
external_clock_interface
clocking
expansion_interface
multiple_device_hardware_synch
rf_shield_installation