From 5c812681ab82b99426152cea2ce9dc3454013e9e Mon Sep 17 00:00:00 2001 From: Michael Ossmann Date: Wed, 21 Sep 2022 04:09:54 -0400 Subject: [PATCH] docs: Remove outdated clocking page --- docs/source/clocking.rst | 38 -------------------------------------- docs/source/index.rst | 1 - 2 files changed, 39 deletions(-) delete mode 100644 docs/source/clocking.rst diff --git a/docs/source/clocking.rst b/docs/source/clocking.rst deleted file mode 100644 index 53f1d960..00000000 --- a/docs/source/clocking.rst +++ /dev/null @@ -1,38 +0,0 @@ -================================================ -Clocking Signals -================================================ - - - -HackRF clock signals are generated by the Si5351. The plan so far: - - * crystal frequency: 25 MHz (supports 25 or 27 MHz) - * optional clock input frequency: 10 MHz recommended (supports 10 to 40 MHz, or higher with division) - * VCO frequency: 800 MHz (supports 600 to 900 MHz) - * MAX2837 clock: 40 MHz - * preferred MAX5864 clocks: 8, 10, 12.5, 16, 20 MHz - * A clock at double the MAX5864 rate will be delivered to the CPLD and SGPIO. - * LPC43xx clock: 12 MHz (from separate crystal so the ROM-based USB DFU will work) - -Lemondrop+Jellybean Si5351 output mapping: - - * CLK0 -> MAX2837 - * CLK1 -> MAX5864/CPLD - * CLK2 -> CPLD - * CLK3 -> CPLD - * CLK4 -> LPC4330 - * CLK5 -> RFFC5072 - * CLK6 -> extra - * CLK7 -> extra - -Jawbreaker output mapping: - - * CLK0 -> MAX5864/CPLD - * CLK1 -> CPLD - * CLK2 -> SGPIO - * CLK3 -> external clock output - * CLK4 -> RFFC5072 - * CLK5 -> MAX2837 - * CLK6 -> none - * CLK7 -> LPC4330 (but LPC4330 will start up on its own crystal) - diff --git a/docs/source/index.rst b/docs/source/index.rst index e8a58c99..8365a591 100644 --- a/docs/source/index.rst +++ b/docs/source/index.rst @@ -42,7 +42,6 @@ Welcome to HackRF's documentation! enclosure_options hackrfs_buttons external_clock_interface - clocking expansion_interface multiple_device_hardware_synch rf_shield_installation