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h1r9: configure MAX2839 HPF

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Without this, the RX baseband gain amplifies a DC offset.
This commit is contained in:
Michael Ossmann
2022-09-25 13:26:05 -04:00
committed by Mike Walters
parent 616705b7e5
commit 3f73290524
2 changed files with 22 additions and 20 deletions
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8
firmware/common/max2839.c
View File

@ -108,13 +108,11 @@ void max2839_setup(max2839_driver_t* const drv)
set_MAX2839_LNA1gain(drv, MAX2839_LNA1gain_M32);
set_MAX2839_Rx1_VGAgain(drv, 0x3f);
//set_MAX2839_TX_VGA_GAIN(drv, 0x18);
/* maximum RX output common-mode voltage */
/* set maximum RX output common-mode voltage */
set_MAX2839_RX_VCM(drv, MAX2839_RX_VCM_1_35);
//FIXME do something with HPFSM/HPC?
//FIXME do something with LPF?
/* set HPF corner frequency to 1 kHz */
set_MAX2839_HPC_STOP(drv, MAX2839_STOP_1K);
max2839_regs_commit(drv);
}

34
firmware/common/max2839_regs.def
View File

@ -131,25 +131,29 @@ __MREG__(MAX2839_RESERVED_10_9,10,9,5)
__MREG__(MAX2839_RESERVED_11_9,11,9,10)
/* REG 12 */
__MREG__(MAX2839_RXVGA_10M_RXEN_duration,12,1,2)
__MREG__(MAX2839_RXVGA_10M_B6B7_duration,12,3,2)
__MREG__(MAX2839_RXVGA_600k_RXEN_duration,12,6,3)
__MREG__(MAX2839_RXVGA_600k_B6B7_duration,12,9,3)
__MREG__(MAX2839_HPC_10M_RXEN_duration,12,1,2)
__MREG__(MAX2839_HPC_10M_B6B7_duration,12,3,2)
__MREG__(MAX2839_HPC_600k_RXEN_duration,12,6,3)
__MREG__(MAX2839_HPC_600k_B6B7_duration,12,9,3)
/* REG 13 */
__MREG__(MAX2839_RXVGA_100k_RXEN_duration,13,1,2)
__MREG__(MAX2839_RXVGA_100k_B6B7_duration,13,3,2)
__MREG__(MAX2839_RXVGA_30k_RXEN_duration,13,5,2)
__MREG__(MAX2839_RXVGA_30k_B6B7_duration,13,7,2)
__MREG__(MAX2839_RXVGA_1k_RXEN_duration,13,9,2)
__MREG__(MAX2839_HPC_100k_RXEN_duration,13,1,2)
__MREG__(MAX2839_HPC_100k_B6B7_duration,13,3,2)
__MREG__(MAX2839_HPC_30k_RXEN_duration,13,5,2)
__MREG__(MAX2839_HPC_30k_B6B7_duration,13,7,2)
__MREG__(MAX2839_HPC_1k_RXEN_duration,13,9,2)
/* REG 14 */
__MREG__(MAX2839_RXVGA_1k_B6B7_duration,14,1,2)
__MREG__(MAX2839_RXVGA_HPCa_HPCd_delay,14,3,2)
__MREG__(MAX2839_RXVGA_final_highpass_corner,14,5,2)
__MREG__(MAX2839_RXVGA_highpass_MODE2,14,7,2)
__MREG__(MAX2839_RXVGA_HPFSM_B6B7,14,8,1)
__MREG__(MAX2839_PA_DRV_DAC,14,9,1)
__MREG__(MAX2839_HPC_1k_B6B7_duration,14,1,2)
__MREG__(MAX2839_HPC_DELAY,14,3,2)
__MREG__(MAX2839_HPC_STOP,14,5,2)
#define MAX2839_STOP_100 0
#define MAX2839_STOP_1K 1
#define MAX2839_STOP_30K 2
#define MAX2839_STOP_100K 3
__MREG__(MAX2839_HPC_STOP_MODE2,14,7,2)
__MREG__(MAX2839_HPC_RXGAIN_EN,14,8,1)
__MREG__(MAX2839_PA_DRV_GATE,14,9,1)
/* REG 15 */
__MREG__(MAX2839_RXVGA_HPFSM_Clk_Divider,15,0,1)