From 3f7329052417fce303a835af5ad6191522f08087 Mon Sep 17 00:00:00 2001 From: Michael Ossmann Date: Sun, 25 Sep 2022 13:26:05 -0400 Subject: [PATCH] h1r9: configure MAX2839 HPF Without this, the RX baseband gain amplifies a DC offset. --- firmware/common/max2839.c | 8 +++----- firmware/common/max2839_regs.def | 34 ++++++++++++++++++-------------- 2 files changed, 22 insertions(+), 20 deletions(-) diff --git a/firmware/common/max2839.c b/firmware/common/max2839.c index 26fef0f7..28cf3ff5 100644 --- a/firmware/common/max2839.c +++ b/firmware/common/max2839.c @@ -108,13 +108,11 @@ void max2839_setup(max2839_driver_t* const drv) set_MAX2839_LNA1gain(drv, MAX2839_LNA1gain_M32); set_MAX2839_Rx1_VGAgain(drv, 0x3f); - //set_MAX2839_TX_VGA_GAIN(drv, 0x18); - - /* maximum RX output common-mode voltage */ + /* set maximum RX output common-mode voltage */ set_MAX2839_RX_VCM(drv, MAX2839_RX_VCM_1_35); - //FIXME do something with HPFSM/HPC? - //FIXME do something with LPF? + /* set HPF corner frequency to 1 kHz */ + set_MAX2839_HPC_STOP(drv, MAX2839_STOP_1K); max2839_regs_commit(drv); } diff --git a/firmware/common/max2839_regs.def b/firmware/common/max2839_regs.def index c857cdd7..8cd578cf 100644 --- a/firmware/common/max2839_regs.def +++ b/firmware/common/max2839_regs.def @@ -131,25 +131,29 @@ __MREG__(MAX2839_RESERVED_10_9,10,9,5) __MREG__(MAX2839_RESERVED_11_9,11,9,10) /* REG 12 */ -__MREG__(MAX2839_RXVGA_10M_RXEN_duration,12,1,2) -__MREG__(MAX2839_RXVGA_10M_B6B7_duration,12,3,2) -__MREG__(MAX2839_RXVGA_600k_RXEN_duration,12,6,3) -__MREG__(MAX2839_RXVGA_600k_B6B7_duration,12,9,3) +__MREG__(MAX2839_HPC_10M_RXEN_duration,12,1,2) +__MREG__(MAX2839_HPC_10M_B6B7_duration,12,3,2) +__MREG__(MAX2839_HPC_600k_RXEN_duration,12,6,3) +__MREG__(MAX2839_HPC_600k_B6B7_duration,12,9,3) /* REG 13 */ -__MREG__(MAX2839_RXVGA_100k_RXEN_duration,13,1,2) -__MREG__(MAX2839_RXVGA_100k_B6B7_duration,13,3,2) -__MREG__(MAX2839_RXVGA_30k_RXEN_duration,13,5,2) -__MREG__(MAX2839_RXVGA_30k_B6B7_duration,13,7,2) -__MREG__(MAX2839_RXVGA_1k_RXEN_duration,13,9,2) +__MREG__(MAX2839_HPC_100k_RXEN_duration,13,1,2) +__MREG__(MAX2839_HPC_100k_B6B7_duration,13,3,2) +__MREG__(MAX2839_HPC_30k_RXEN_duration,13,5,2) +__MREG__(MAX2839_HPC_30k_B6B7_duration,13,7,2) +__MREG__(MAX2839_HPC_1k_RXEN_duration,13,9,2) /* REG 14 */ -__MREG__(MAX2839_RXVGA_1k_B6B7_duration,14,1,2) -__MREG__(MAX2839_RXVGA_HPCa_HPCd_delay,14,3,2) -__MREG__(MAX2839_RXVGA_final_highpass_corner,14,5,2) -__MREG__(MAX2839_RXVGA_highpass_MODE2,14,7,2) -__MREG__(MAX2839_RXVGA_HPFSM_B6B7,14,8,1) -__MREG__(MAX2839_PA_DRV_DAC,14,9,1) +__MREG__(MAX2839_HPC_1k_B6B7_duration,14,1,2) +__MREG__(MAX2839_HPC_DELAY,14,3,2) +__MREG__(MAX2839_HPC_STOP,14,5,2) +#define MAX2839_STOP_100 0 +#define MAX2839_STOP_1K 1 +#define MAX2839_STOP_30K 2 +#define MAX2839_STOP_100K 3 +__MREG__(MAX2839_HPC_STOP_MODE2,14,7,2) +__MREG__(MAX2839_HPC_RXGAIN_EN,14,8,1) +__MREG__(MAX2839_PA_DRV_GATE,14,9,1) /* REG 15 */ __MREG__(MAX2839_RXVGA_HPFSM_Clk_Divider,15,0,1)