max2837: updates
- band setting in set_frequency() - rework init() to copy default settings from static data - tweak some awkward naming in reg defs to be equally awkward but consistent
This commit is contained in:
Will Code
@ -5,7 +5,9 @@
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* 'gcc -DTEST -DBUS_PIRATE -O2 -o test max2837.c' prints out bus
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* pirate commands to do the same thing.
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*/
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#include <stdint.h>
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#include <string.h>
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#include "max2837.h"
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#include "max2837_regs.def" // private register def macros
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@ -16,7 +18,8 @@
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#define LOG(x,...)
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#endif
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uint16_t max2837_regs[MAX2837_NUM_REGS] = {
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/* Default register values. */
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static uint16_t max2837_regs_default[MAX2837_NUM_REGS] = {
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0x150, /* 0 */
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0x002, /* 1 */
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0x1f4, /* 2 */
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@ -50,13 +53,15 @@ uint16_t max2837_regs[MAX2837_NUM_REGS] = {
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0x080, /* 30 */
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0x000 }; /* 31 */
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uint16_t max2837_regs[MAX2837_NUM_REGS];
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/* Mark all regsisters dirty so all will be written at init. */
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uint32_t max2837_regs_dirty = 0xffffffff;
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void max2837_init(void)
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{
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LOG("# max2837_init\n");
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/* TODO - reset all register values to defaults? Where from? */
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memcpy(max2837_regs, max2837_regs_default, sizeof(max2837_regs));
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max2837_regs_dirty = 0xffffffff;
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/* Write default register values to chip. */
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@ -96,6 +101,7 @@ void max2837_reg_write(uint8_t r, uint16_t v)
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MAX2837_REG_SET_CLEAN(r);
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}
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/* This functions should not be needed, and might be confusing. DELETE. */
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void max2837_regs_read(void)
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{
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;
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@ -135,6 +141,7 @@ void max2837_stop(void)
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void max2837_set_frequency(uint32_t freq)
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{
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uint8_t band;
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uint8_t lna_band;
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uint32_t div_frac;
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uint32_t div_int;
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uint32_t div_rem;
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@ -142,16 +149,25 @@ void max2837_set_frequency(uint32_t freq)
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int i;
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/* Select band. Allow tuning outside specified bands. */
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if (freq < 2400000000)
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if (freq < 2400000000) {
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band = MAX2837_LOGEN_BSW_2_3;
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else if (freq < 2500000000)
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lna_band = MAX2837_LNAband_2_4;
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}
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else if (freq < 2500000000) {
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band = MAX2837_LOGEN_BSW_2_4;
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else if (freq < 2600000000)
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lna_band = MAX2837_LNAband_2_4;
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}
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else if (freq < 2600000000) {
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band = MAX2837_LOGEN_BSW_2_5;
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else
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lna_band = MAX2837_LNAband_2_6;
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}
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else {
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band = MAX2837_LOGEN_BSW_2_6;
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lna_band = MAX2837_LNAband_2_6;
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}
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LOG("# max2837_set_frequency %ld, band %d\n", freq, band);
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LOG("# max2837_set_frequency %ld, band %d, lna band %d\n",
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freq, band, lna_band);
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/* ASSUME 40MHz PLL. Ratio = F*(4/3)/40,000,000 = F/30,000,000 */
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div_int = freq / 30000000;
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@ -168,7 +184,9 @@ void max2837_set_frequency(uint32_t freq)
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}
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LOG("# int %ld, frac %ld\n", div_int, div_frac);
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//
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/* Band settings */
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set_MAX2837_LOGEN_BSW(band);
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set_MAX2837_LNAband(lna_band);
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/* Write order matters here, so commit INT and FRAC_HI before
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* committing FRAC_LO, which is the trigger for VCO
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@ -235,11 +235,11 @@ __MREG__(MAX2837_LOGEN_BSW,19,9,2)
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__MREG__(MAX2837_SYN_MODE,20,0,1)
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#define MAX2837_SYN_MODE_INTEGER 0
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#define MAX2837_SYN_MODE_FRACTIONAL 1
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__MREG__(MAX2837_SYN_DIV,20,2,2)
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#define MAX2837_SYN_DIV_1 0
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#define MAX2837_SYN_DIV_2 1
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#define MAX2837_SYN_DIV_4 2
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#define MAX2837_SYN_DIV_8 3
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__MREG__(MAX2837_SYN_REF_DIV,20,2,2)
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#define MAX2837_SYN_REF_DIV_1 0
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#define MAX2837_SYN_REF_DIV_2 1
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#define MAX2837_SYN_REF_DIV_4 2
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#define MAX2837_SYN_REF_DIV_8 3
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__MREG__(MAX2837_SYN_CURRENT_,20,4,2)
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#define MAX2837_SYN_CURRENT_3_2_DIFF 0 // 3.2mA differential
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#define MAX2837_SYN_CURRENT_1_6_DIFF 1 // 1.6mA differential
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@ -272,7 +272,7 @@ __MREG__(MAX2837_SYN_TEST_OUT,21,9,3) // high bit locks CP in test mode
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#define MAX2837_SYN_TEST_CP_HI_Z_MAIN_DIV 0b111
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/* REG 22 */
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__MREG__(MAX2837_VAS_EN,22,0,1)
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__MREG__(MAX2837_VAS_EN,22,0,1) // select VCO subband by VAS, vs. reg
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__MREG__(MAX2837_VAS_RELOCK_SEL,22,1,1)
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#define MAX2837_VAS_RELOCK_SELECTED 0
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#define MAX2837_VAS_RELOCK_PRESENT 1
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@ -311,14 +311,14 @@ __MREG__(MAX2837_VCO_SPI_EN,23,9,1) // set to override mode
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/* REG 24 */
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__MREG__(MAX2837_XTAL_TUNE,24,6,7) // 0=max 127=min freq
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__MREG__(MAX2837_CLKOUT_EN,24,7,1)
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__MREG__(MAX2837_CLKOUT_PIN_EN,24,7,1)
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__MREG__(MAX2837_CLKOUT_DIV,24,8,1)
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#define MAX2837_CLKOUT_DIV_1 0
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#define MAX2837_CLKOUT_DIV_2 1
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__MREG__(MAX2837_XTAL_EN,24,9,1) // set to override mode
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__MREG__(MAX2837_XTAL_CORE_EN,24,9,1) // set to override mode
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/* REG 25 */
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__MREG__(MAX2837_VCO_BIAS_EN,25,0,1) // enable override of vco bias trim
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__MREG__(MAX2837_VCO_BIAS_SPI_EN,25,0,1) // enable override of vco bias trim
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__MREG__(MAX2837_VCO_BIAS,25,4,4) // 0b1000 nominal
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__MREG__(MAX2837_VCO_CMEN,25,5,1) // enable Miller capacitor
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__MREG__(MAX2837_VCO_PDET_TST,25,7,2) // peak detector test output select
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@ -359,7 +359,7 @@ __MREG__(MAX2837_VAS_TST,26,9,4) // DOUT test signal select
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/* REG 27 */
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__MREG__(MAX2837_PADRV_BIAS,27,2,3) // PA driver bias (0-7), default 3
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__MREG__(MAX2837_PADRV_DOWN_EN,27,3,1) // PA driver down process select enable
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__MREG__(MAX2837_PADRV_DOWN_SPI_EN,27,3,1) // PA drv down process select enable
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__MREG__(MAX2837_PADRV_DOWN,27,4,1) // PA driver down select
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#define MAX2837_PADRV_DOWN_DOWN 0
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#define MAX2837_PADRV_DOWN_UP 1 // default
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@ -380,15 +380,15 @@ __MREG__(MAX2837_PADAC_DLY,28,9,4) // PADAC turn-on delay control
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// then 0.5us steps to 7.0us
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/* REG 29 */
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__MREG__(MAX2837_TXVGA_GAIN_EN,29,0,1) // Enable SPI control of TXVGA gain
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__MREG__(MAX2837_TXVGA_GAIN_MSB_EN,29,1,1)
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__MREG__(MAX2837_TX_DCCORR_EN,29,2,1)
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__MREG__(MAX2837_TXVGA_GAIN_SPI_EN,29,0,1) // Enable SPI control of TXVGA gain
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__MREG__(MAX2837_TXVGA_GAIN_MSB_SPI_EN,29,1,1)
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__MREG__(MAX2837_TX_DCCORR_SPI_EN,29,2,1)
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__MREG__(MAX2837_FUSE_ARM,29,3,1) // Fuse burn enable
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__MREG__(MAX2837_TXVGA_GAIN,29,5,6) // 0 = min atten, 63 = max atten
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/* REG 30 */
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__MREG__(MAX2837_TXLO_IQ,30,4,5)
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__MREG__(MAX2837_TXLO_IQ_EN,30,5,5)
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__MREG__(MAX2837_TXLO_IQ_SPI_EN,30,5,5)
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__MREG__(MAX2837_TXLO_BUFF_BIAS,30,7,2)
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#define MAX2837_TXLO_BUFF_BIAS_1_0mA 0
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#define MAX2837_TXLO_BUFF_BIAS_1_5mA 1
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@ -398,7 +398,7 @@ __MREG__(MAX2837_FUSE_GKT,30,8,1)
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__MREG__(MAX2837_FUSE_RTH,30,9,1)
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/* REG 31 */
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// 0 -> 992/0uA correction, 15 -> 0/992uA correction ... if TX_DCCORR_EN
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// 0 -> 992/0uA correction, 15 -> 0/992uA correction ... if TX_DCCORR_SPI_EN
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__MREG__(MAX2837_TX_DCCORR_I,31,4,5)
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__MREG__(MAX2837_TX_DCCORR_Q,31,9,5)
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