From 1b806c75e98c091e8320bc8519576f02a212bb0a Mon Sep 17 00:00:00 2001 From: Will Code Date: Mon, 4 Jun 2012 18:48:42 -0400 Subject: [PATCH] max2837: updates - band setting in set_frequency() - rework init() to copy default settings from static data - tweak some awkward naming in reg defs to be equally awkward but consistent --- firmware/common/max2837.c | 34 ++++++++++++++++++++++++-------- firmware/common/max2837_regs.def | 30 ++++++++++++++-------------- 2 files changed, 41 insertions(+), 23 deletions(-) diff --git a/firmware/common/max2837.c b/firmware/common/max2837.c index 7a27c55c..3617a81a 100644 --- a/firmware/common/max2837.c +++ b/firmware/common/max2837.c @@ -5,7 +5,9 @@ * 'gcc -DTEST -DBUS_PIRATE -O2 -o test max2837.c' prints out bus * pirate commands to do the same thing. */ + #include +#include #include "max2837.h" #include "max2837_regs.def" // private register def macros @@ -16,7 +18,8 @@ #define LOG(x,...) #endif -uint16_t max2837_regs[MAX2837_NUM_REGS] = { +/* Default register values. */ +static uint16_t max2837_regs_default[MAX2837_NUM_REGS] = { 0x150, /* 0 */ 0x002, /* 1 */ 0x1f4, /* 2 */ @@ -50,13 +53,15 @@ uint16_t max2837_regs[MAX2837_NUM_REGS] = { 0x080, /* 30 */ 0x000 }; /* 31 */ +uint16_t max2837_regs[MAX2837_NUM_REGS]; + /* Mark all regsisters dirty so all will be written at init. */ uint32_t max2837_regs_dirty = 0xffffffff; void max2837_init(void) { LOG("# max2837_init\n"); - /* TODO - reset all register values to defaults? Where from? */ + memcpy(max2837_regs, max2837_regs_default, sizeof(max2837_regs)); max2837_regs_dirty = 0xffffffff; /* Write default register values to chip. */ @@ -96,6 +101,7 @@ void max2837_reg_write(uint8_t r, uint16_t v) MAX2837_REG_SET_CLEAN(r); } +/* This functions should not be needed, and might be confusing. DELETE. */ void max2837_regs_read(void) { ; @@ -135,6 +141,7 @@ void max2837_stop(void) void max2837_set_frequency(uint32_t freq) { uint8_t band; + uint8_t lna_band; uint32_t div_frac; uint32_t div_int; uint32_t div_rem; @@ -142,16 +149,25 @@ void max2837_set_frequency(uint32_t freq) int i; /* Select band. Allow tuning outside specified bands. */ - if (freq < 2400000000) + if (freq < 2400000000) { band = MAX2837_LOGEN_BSW_2_3; - else if (freq < 2500000000) + lna_band = MAX2837_LNAband_2_4; + } + else if (freq < 2500000000) { band = MAX2837_LOGEN_BSW_2_4; - else if (freq < 2600000000) + lna_band = MAX2837_LNAband_2_4; + } + else if (freq < 2600000000) { band = MAX2837_LOGEN_BSW_2_5; - else + lna_band = MAX2837_LNAband_2_6; + } + else { band = MAX2837_LOGEN_BSW_2_6; + lna_band = MAX2837_LNAband_2_6; + } - LOG("# max2837_set_frequency %ld, band %d\n", freq, band); + LOG("# max2837_set_frequency %ld, band %d, lna band %d\n", + freq, band, lna_band); /* ASSUME 40MHz PLL. Ratio = F*(4/3)/40,000,000 = F/30,000,000 */ div_int = freq / 30000000; @@ -168,7 +184,9 @@ void max2837_set_frequency(uint32_t freq) } LOG("# int %ld, frac %ld\n", div_int, div_frac); -// + /* Band settings */ + set_MAX2837_LOGEN_BSW(band); + set_MAX2837_LNAband(lna_band); /* Write order matters here, so commit INT and FRAC_HI before * committing FRAC_LO, which is the trigger for VCO diff --git a/firmware/common/max2837_regs.def b/firmware/common/max2837_regs.def index 4042afd2..c3de2b35 100644 --- a/firmware/common/max2837_regs.def +++ b/firmware/common/max2837_regs.def @@ -235,11 +235,11 @@ __MREG__(MAX2837_LOGEN_BSW,19,9,2) __MREG__(MAX2837_SYN_MODE,20,0,1) #define MAX2837_SYN_MODE_INTEGER 0 #define MAX2837_SYN_MODE_FRACTIONAL 1 -__MREG__(MAX2837_SYN_DIV,20,2,2) -#define MAX2837_SYN_DIV_1 0 -#define MAX2837_SYN_DIV_2 1 -#define MAX2837_SYN_DIV_4 2 -#define MAX2837_SYN_DIV_8 3 +__MREG__(MAX2837_SYN_REF_DIV,20,2,2) +#define MAX2837_SYN_REF_DIV_1 0 +#define MAX2837_SYN_REF_DIV_2 1 +#define MAX2837_SYN_REF_DIV_4 2 +#define MAX2837_SYN_REF_DIV_8 3 __MREG__(MAX2837_SYN_CURRENT_,20,4,2) #define MAX2837_SYN_CURRENT_3_2_DIFF 0 // 3.2mA differential #define MAX2837_SYN_CURRENT_1_6_DIFF 1 // 1.6mA differential @@ -272,7 +272,7 @@ __MREG__(MAX2837_SYN_TEST_OUT,21,9,3) // high bit locks CP in test mode #define MAX2837_SYN_TEST_CP_HI_Z_MAIN_DIV 0b111 /* REG 22 */ -__MREG__(MAX2837_VAS_EN,22,0,1) +__MREG__(MAX2837_VAS_EN,22,0,1) // select VCO subband by VAS, vs. reg __MREG__(MAX2837_VAS_RELOCK_SEL,22,1,1) #define MAX2837_VAS_RELOCK_SELECTED 0 #define MAX2837_VAS_RELOCK_PRESENT 1 @@ -311,14 +311,14 @@ __MREG__(MAX2837_VCO_SPI_EN,23,9,1) // set to override mode /* REG 24 */ __MREG__(MAX2837_XTAL_TUNE,24,6,7) // 0=max 127=min freq -__MREG__(MAX2837_CLKOUT_EN,24,7,1) +__MREG__(MAX2837_CLKOUT_PIN_EN,24,7,1) __MREG__(MAX2837_CLKOUT_DIV,24,8,1) #define MAX2837_CLKOUT_DIV_1 0 #define MAX2837_CLKOUT_DIV_2 1 -__MREG__(MAX2837_XTAL_EN,24,9,1) // set to override mode +__MREG__(MAX2837_XTAL_CORE_EN,24,9,1) // set to override mode /* REG 25 */ -__MREG__(MAX2837_VCO_BIAS_EN,25,0,1) // enable override of vco bias trim +__MREG__(MAX2837_VCO_BIAS_SPI_EN,25,0,1) // enable override of vco bias trim __MREG__(MAX2837_VCO_BIAS,25,4,4) // 0b1000 nominal __MREG__(MAX2837_VCO_CMEN,25,5,1) // enable Miller capacitor __MREG__(MAX2837_VCO_PDET_TST,25,7,2) // peak detector test output select @@ -359,7 +359,7 @@ __MREG__(MAX2837_VAS_TST,26,9,4) // DOUT test signal select /* REG 27 */ __MREG__(MAX2837_PADRV_BIAS,27,2,3) // PA driver bias (0-7), default 3 -__MREG__(MAX2837_PADRV_DOWN_EN,27,3,1) // PA driver down process select enable +__MREG__(MAX2837_PADRV_DOWN_SPI_EN,27,3,1) // PA drv down process select enable __MREG__(MAX2837_PADRV_DOWN,27,4,1) // PA driver down select #define MAX2837_PADRV_DOWN_DOWN 0 #define MAX2837_PADRV_DOWN_UP 1 // default @@ -380,15 +380,15 @@ __MREG__(MAX2837_PADAC_DLY,28,9,4) // PADAC turn-on delay control // then 0.5us steps to 7.0us /* REG 29 */ -__MREG__(MAX2837_TXVGA_GAIN_EN,29,0,1) // Enable SPI control of TXVGA gain -__MREG__(MAX2837_TXVGA_GAIN_MSB_EN,29,1,1) -__MREG__(MAX2837_TX_DCCORR_EN,29,2,1) +__MREG__(MAX2837_TXVGA_GAIN_SPI_EN,29,0,1) // Enable SPI control of TXVGA gain +__MREG__(MAX2837_TXVGA_GAIN_MSB_SPI_EN,29,1,1) +__MREG__(MAX2837_TX_DCCORR_SPI_EN,29,2,1) __MREG__(MAX2837_FUSE_ARM,29,3,1) // Fuse burn enable __MREG__(MAX2837_TXVGA_GAIN,29,5,6) // 0 = min atten, 63 = max atten /* REG 30 */ __MREG__(MAX2837_TXLO_IQ,30,4,5) -__MREG__(MAX2837_TXLO_IQ_EN,30,5,5) +__MREG__(MAX2837_TXLO_IQ_SPI_EN,30,5,5) __MREG__(MAX2837_TXLO_BUFF_BIAS,30,7,2) #define MAX2837_TXLO_BUFF_BIAS_1_0mA 0 #define MAX2837_TXLO_BUFF_BIAS_1_5mA 1 @@ -398,7 +398,7 @@ __MREG__(MAX2837_FUSE_GKT,30,8,1) __MREG__(MAX2837_FUSE_RTH,30,9,1) /* REG 31 */ -// 0 -> 992/0uA correction, 15 -> 0/992uA correction ... if TX_DCCORR_EN +// 0 -> 992/0uA correction, 15 -> 0/992uA correction ... if TX_DCCORR_SPI_EN __MREG__(MAX2837_TX_DCCORR_I,31,4,5) __MREG__(MAX2837_TX_DCCORR_Q,31,9,5)