Merge pull request #121 from jboone/cleanup_201408
Miscellaneous clean-up
This commit is contained in:
@ -33,9 +33,6 @@ int main(void)
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/* enable all power supplies */
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/* enable all power supplies */
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enable_1v8_power();
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enable_1v8_power();
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#ifdef HACKRF_ONE
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enable_rf_power();
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#endif
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/* Blink LED1/2/3 on the board and Read BOOT0/1/2/3 pins. */
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/* Blink LED1/2/3 on the board and Read BOOT0/1/2/3 pins. */
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while (1)
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while (1)
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@ -47,7 +47,7 @@ void hard_fault_handler(void) {
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volatile hard_fault_stack_t* hard_fault_stack_pt;
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volatile hard_fault_stack_t* hard_fault_stack_pt;
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void hard_fault_handler_c(uint32_t* args)
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__attribute__((used)) void hard_fault_handler_c(uint32_t* args)
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{
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{
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/* hard_fault_stack_pt contains registers saved before the hard fault */
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/* hard_fault_stack_pt contains registers saved before the hard fault */
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hard_fault_stack_pt = (hard_fault_stack_t*)args;
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hard_fault_stack_pt = (hard_fault_stack_t*)args;
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@ -261,6 +261,9 @@ void cpu_clock_init(void)
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/* use IRC as clock source for APB1 (including I2C0) */
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/* use IRC as clock source for APB1 (including I2C0) */
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CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_IRC);
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CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_IRC);
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/* use IRC as clock source for APB3 */
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CGU_BASE_APB3_CLK = CGU_BASE_APB3_CLK_CLK_SEL(CGU_SRC_IRC);
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i2c0_init(15);
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i2c0_init(15);
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si5351c_disable_all_outputs();
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si5351c_disable_all_outputs();
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@ -365,6 +368,10 @@ void cpu_clock_init(void)
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CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_AUTOBLOCK(1)
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CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_AUTOBLOCK(1)
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| CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_XTAL);
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| CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_XTAL);
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/* use XTAL_OSC as clock source for APB3 */
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CGU_BASE_APB3_CLK = CGU_BASE_APB3_CLK_AUTOBLOCK(1)
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| CGU_BASE_APB3_CLK_CLK_SEL(CGU_SRC_XTAL);
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cpu_clock_pll1_low_speed();
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cpu_clock_pll1_low_speed();
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/* use PLL1 as clock source for BASE_M4_CLK (CPU) */
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/* use PLL1 as clock source for BASE_M4_CLK (CPU) */
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@ -400,6 +407,10 @@ void cpu_clock_init(void)
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/* Switch APB1 clock over to use PLL1 (204MHz) */
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/* Switch APB1 clock over to use PLL1 (204MHz) */
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CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_AUTOBLOCK(1)
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CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_AUTOBLOCK(1)
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| CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_PLL1);
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| CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_PLL1);
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/* Switch APB3 clock over to use PLL1 (204MHz) */
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CGU_BASE_APB3_CLK = CGU_BASE_APB3_CLK_AUTOBLOCK(1)
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| CGU_BASE_APB3_CLK_CLK_SEL(CGU_SRC_PLL1);
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}
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}
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@ -578,14 +589,11 @@ void pin_setup(void) {
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scu_pinmux(SCU_PINMUX_EN1V8, SCU_GPIO_NOPULL);
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scu_pinmux(SCU_PINMUX_EN1V8, SCU_GPIO_NOPULL);
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scu_pinmux(SCU_PINMUX_BOOT0, SCU_GPIO_FAST);
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scu_pinmux(SCU_PINMUX_BOOT1, SCU_GPIO_FAST);
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scu_pinmux(SCU_PINMUX_BOOT2, SCU_GPIO_FAST);
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scu_pinmux(SCU_PINMUX_BOOT3, SCU_GPIO_FAST);
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/* Configure USB indicators */
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/* Configure USB indicators */
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#if (defined JELLYBEAN || defined JAWBREAKER)
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scu_pinmux(SCU_PINMUX_USB_LED0, SCU_CONF_FUNCTION3);
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scu_pinmux(SCU_PINMUX_USB_LED0, SCU_CONF_FUNCTION3);
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scu_pinmux(SCU_PINMUX_USB_LED1, SCU_CONF_FUNCTION3);
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scu_pinmux(SCU_PINMUX_USB_LED1, SCU_CONF_FUNCTION3);
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#endif
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/* Configure all GPIO as Input (safe state) */
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/* Configure all GPIO as Input (safe state) */
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GPIO0_DIR = 0;
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GPIO0_DIR = 0;
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@ -67,8 +67,10 @@ extern "C"
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#define SCU_PINMUX_BOOT3 (P2_9) /* GPIO1[10] on P2_9 */
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#define SCU_PINMUX_BOOT3 (P2_9) /* GPIO1[10] on P2_9 */
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/* USB peripheral */
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/* USB peripheral */
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#if (defined JELLYBEAN || defined JAWBREAKER)
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#define SCU_PINMUX_USB_LED0 (P6_8)
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#define SCU_PINMUX_USB_LED0 (P6_8)
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#define SCU_PINMUX_USB_LED1 (P6_7)
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#define SCU_PINMUX_USB_LED1 (P6_7)
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#endif
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/* SSP1 Peripheral PinMux */
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/* SSP1 Peripheral PinMux */
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#define SCU_SSP1_MISO (P1_3) /* P1_3 */
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#define SCU_SSP1_MISO (P1_3) /* P1_3 */
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@ -114,7 +114,7 @@ bool set_freq_explicit(const uint64_t if_freq_hz, const uint64_t lo_freq_hz,
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}
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}
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if ((path != RF_PATH_FILTER_BYPASS) &&
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if ((path != RF_PATH_FILTER_BYPASS) &&
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(lo_freq_hz < MIN_LO_FREQ_HZ) || (lo_freq_hz > MAX_LO_FREQ_HZ)) {
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((lo_freq_hz < MIN_LO_FREQ_HZ) || (lo_freq_hz > MAX_LO_FREQ_HZ))) {
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return false;
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return false;
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}
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}
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@ -33,7 +33,10 @@ int main(void)
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const uint32_t freq = 2441000000U;
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const uint32_t freq = 2441000000U;
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pin_setup();
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pin_setup();
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gpio_set(PORT_EN1V8, PIN_EN1V8); /* 1V8 on */
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enable_1v8_power();
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#ifdef HACKRF_ONE
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enable_rf_power();
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#endif
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cpu_clock_init();
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cpu_clock_init();
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ssp1_init();
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ssp1_init();
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@ -92,6 +92,9 @@ int main(void) {
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pin_setup();
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pin_setup();
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enable_1v8_power();
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enable_1v8_power();
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#ifdef HACKRF_ONE
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enable_rf_power();
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#endif
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cpu_clock_init();
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cpu_clock_init();
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ssp1_init();
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ssp1_init();
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rf_path_init();
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rf_path_init();
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@ -32,7 +32,10 @@ int main(void)
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const uint32_t freq = 2441000000U;
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const uint32_t freq = 2441000000U;
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pin_setup();
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pin_setup();
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gpio_set(PORT_EN1V8, PIN_EN1V8); /* 1V8 on */
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enable_1v8_power();
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#ifdef HACKRF_ONE
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enable_rf_power();
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#endif
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cpu_clock_init();
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cpu_clock_init();
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ssp1_init();
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ssp1_init();
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@ -32,8 +32,7 @@ int main(void)
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pin_setup();
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pin_setup();
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/* Set 1V8 */
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enable_1v8_power();
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gpio_set(PORT_EN1V8, PIN_EN1V8);
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cpu_clock_init();
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cpu_clock_init();
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@ -31,7 +31,7 @@ int main(void)
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pin_setup();
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pin_setup();
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gpio_set(PORT_EN1V8, PIN_EN1V8); /* 1V8 on */
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enable_1v8_power();
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cpu_clock_init();
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cpu_clock_init();
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@ -131,7 +131,7 @@ int main(void)
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{
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{
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pin_setup();
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pin_setup();
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gpio_set(PORT_EN1V8, PIN_EN1V8); /* 1V8 on */
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enable_1v8_power();
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cpu_clock_init();
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cpu_clock_init();
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@ -144,7 +144,7 @@ int main(void)
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{
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{
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pin_setup();
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pin_setup();
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gpio_set(PORT_EN1V8, PIN_EN1V8); /* 1V8 on */
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enable_1v8_power();
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cpu_clock_init();
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cpu_clock_init();
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