diff --git a/firmware/blinky/blinky.c b/firmware/blinky/blinky.c index 77be8339..0201cff4 100644 --- a/firmware/blinky/blinky.c +++ b/firmware/blinky/blinky.c @@ -33,9 +33,6 @@ int main(void) /* enable all power supplies */ enable_1v8_power(); -#ifdef HACKRF_ONE - enable_rf_power(); -#endif /* Blink LED1/2/3 on the board and Read BOOT0/1/2/3 pins. */ while (1) diff --git a/firmware/common/fault_handler.c b/firmware/common/fault_handler.c index 50331335..c43a2f50 100644 --- a/firmware/common/fault_handler.c +++ b/firmware/common/fault_handler.c @@ -47,7 +47,7 @@ void hard_fault_handler(void) { volatile hard_fault_stack_t* hard_fault_stack_pt; -void hard_fault_handler_c(uint32_t* args) +__attribute__((used)) void hard_fault_handler_c(uint32_t* args) { /* hard_fault_stack_pt contains registers saved before the hard fault */ hard_fault_stack_pt = (hard_fault_stack_t*)args; diff --git a/firmware/common/hackrf_core.c b/firmware/common/hackrf_core.c index dc4c4708..b862ba4f 100644 --- a/firmware/common/hackrf_core.c +++ b/firmware/common/hackrf_core.c @@ -261,6 +261,9 @@ void cpu_clock_init(void) /* use IRC as clock source for APB1 (including I2C0) */ CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_IRC); + /* use IRC as clock source for APB3 */ + CGU_BASE_APB3_CLK = CGU_BASE_APB3_CLK_CLK_SEL(CGU_SRC_IRC); + i2c0_init(15); si5351c_disable_all_outputs(); @@ -365,6 +368,10 @@ void cpu_clock_init(void) CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_AUTOBLOCK(1) | CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_XTAL); + /* use XTAL_OSC as clock source for APB3 */ + CGU_BASE_APB3_CLK = CGU_BASE_APB3_CLK_AUTOBLOCK(1) + | CGU_BASE_APB3_CLK_CLK_SEL(CGU_SRC_XTAL); + cpu_clock_pll1_low_speed(); /* use PLL1 as clock source for BASE_M4_CLK (CPU) */ @@ -400,6 +407,10 @@ void cpu_clock_init(void) /* Switch APB1 clock over to use PLL1 (204MHz) */ CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_AUTOBLOCK(1) | CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_PLL1); + + /* Switch APB3 clock over to use PLL1 (204MHz) */ + CGU_BASE_APB3_CLK = CGU_BASE_APB3_CLK_AUTOBLOCK(1) + | CGU_BASE_APB3_CLK_CLK_SEL(CGU_SRC_PLL1); } @@ -578,14 +589,11 @@ void pin_setup(void) { scu_pinmux(SCU_PINMUX_EN1V8, SCU_GPIO_NOPULL); - scu_pinmux(SCU_PINMUX_BOOT0, SCU_GPIO_FAST); - scu_pinmux(SCU_PINMUX_BOOT1, SCU_GPIO_FAST); - scu_pinmux(SCU_PINMUX_BOOT2, SCU_GPIO_FAST); - scu_pinmux(SCU_PINMUX_BOOT3, SCU_GPIO_FAST); - /* Configure USB indicators */ +#if (defined JELLYBEAN || defined JAWBREAKER) scu_pinmux(SCU_PINMUX_USB_LED0, SCU_CONF_FUNCTION3); scu_pinmux(SCU_PINMUX_USB_LED1, SCU_CONF_FUNCTION3); +#endif /* Configure all GPIO as Input (safe state) */ GPIO0_DIR = 0; diff --git a/firmware/common/hackrf_core.h b/firmware/common/hackrf_core.h index 0b9a833b..8ce6c943 100644 --- a/firmware/common/hackrf_core.h +++ b/firmware/common/hackrf_core.h @@ -67,8 +67,10 @@ extern "C" #define SCU_PINMUX_BOOT3 (P2_9) /* GPIO1[10] on P2_9 */ /* USB peripheral */ +#if (defined JELLYBEAN || defined JAWBREAKER) #define SCU_PINMUX_USB_LED0 (P6_8) #define SCU_PINMUX_USB_LED1 (P6_7) +#endif /* SSP1 Peripheral PinMux */ #define SCU_SSP1_MISO (P1_3) /* P1_3 */ diff --git a/firmware/common/tuning.c b/firmware/common/tuning.c index 050a0602..921c1916 100644 --- a/firmware/common/tuning.c +++ b/firmware/common/tuning.c @@ -114,7 +114,7 @@ bool set_freq_explicit(const uint64_t if_freq_hz, const uint64_t lo_freq_hz, } if ((path != RF_PATH_FILTER_BYPASS) && - (lo_freq_hz < MIN_LO_FREQ_HZ) || (lo_freq_hz > MAX_LO_FREQ_HZ)) { + ((lo_freq_hz < MIN_LO_FREQ_HZ) || (lo_freq_hz > MAX_LO_FREQ_HZ))) { return false; } diff --git a/firmware/mixertx/mixertx.c b/firmware/mixertx/mixertx.c index 18415944..363859f5 100644 --- a/firmware/mixertx/mixertx.c +++ b/firmware/mixertx/mixertx.c @@ -33,7 +33,10 @@ int main(void) const uint32_t freq = 2441000000U; pin_setup(); - gpio_set(PORT_EN1V8, PIN_EN1V8); /* 1V8 on */ + enable_1v8_power(); +#ifdef HACKRF_ONE + enable_rf_power(); +#endif cpu_clock_init(); ssp1_init(); diff --git a/firmware/sgpio-rx/sgpio-rx.c b/firmware/sgpio-rx/sgpio-rx.c index a5fb1e86..dbee1d3f 100644 --- a/firmware/sgpio-rx/sgpio-rx.c +++ b/firmware/sgpio-rx/sgpio-rx.c @@ -92,6 +92,9 @@ int main(void) { pin_setup(); enable_1v8_power(); +#ifdef HACKRF_ONE + enable_rf_power(); +#endif cpu_clock_init(); ssp1_init(); rf_path_init(); diff --git a/firmware/simpletx/simpletx.c b/firmware/simpletx/simpletx.c index e50fbf54..04efb686 100644 --- a/firmware/simpletx/simpletx.c +++ b/firmware/simpletx/simpletx.c @@ -32,7 +32,10 @@ int main(void) const uint32_t freq = 2441000000U; pin_setup(); - gpio_set(PORT_EN1V8, PIN_EN1V8); /* 1V8 on */ + enable_1v8_power(); +#ifdef HACKRF_ONE + enable_rf_power(); +#endif cpu_clock_init(); ssp1_init(); diff --git a/firmware/spiflash/spiflash.c b/firmware/spiflash/spiflash.c index 0e8546e4..e1ae772e 100644 --- a/firmware/spiflash/spiflash.c +++ b/firmware/spiflash/spiflash.c @@ -32,8 +32,7 @@ int main(void) pin_setup(); - /* Set 1V8 */ - gpio_set(PORT_EN1V8, PIN_EN1V8); + enable_1v8_power(); cpu_clock_init(); diff --git a/firmware/startup/startup.c b/firmware/startup/startup.c index 71a62010..b6d0be65 100644 --- a/firmware/startup/startup.c +++ b/firmware/startup/startup.c @@ -31,7 +31,7 @@ int main(void) pin_setup(); - gpio_set(PORT_EN1V8, PIN_EN1V8); /* 1V8 on */ + enable_1v8_power(); cpu_clock_init(); diff --git a/firmware/startup_systick/startup_systick.c b/firmware/startup_systick/startup_systick.c index 5a38d2e6..d4c8517e 100644 --- a/firmware/startup_systick/startup_systick.c +++ b/firmware/startup_systick/startup_systick.c @@ -131,7 +131,7 @@ int main(void) { pin_setup(); - gpio_set(PORT_EN1V8, PIN_EN1V8); /* 1V8 on */ + enable_1v8_power(); cpu_clock_init(); diff --git a/firmware/startup_systick_perfo/startup_systick.c b/firmware/startup_systick_perfo/startup_systick.c index 3aea48fd..26c1fcc0 100644 --- a/firmware/startup_systick_perfo/startup_systick.c +++ b/firmware/startup_systick_perfo/startup_systick.c @@ -144,7 +144,7 @@ int main(void) { pin_setup(); - gpio_set(PORT_EN1V8, PIN_EN1V8); /* 1V8 on */ + enable_1v8_power(); cpu_clock_init();