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Oops, read PLL1 documentation again. Looks like FBSEL=1 is for "normal operation". So include that, but use DIRECT=1 to skip the PSEL divider (which would prevent us producing 204MHz from an in-spec PLL frequency).

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Jared Boone
2013-05-11 12:25:54 -07:00
parent e065cdfe20
commit 1723cd12a1
1 changed files with 1 additions and 0 deletions
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firmware/common/hackrf_core.c
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@ -252,6 +252,7 @@ void cpu_clock_init(void)
| CGU_PLL1_CTRL_PSEL(0) | CGU_PLL1_CTRL_PSEL(0)
| CGU_PLL1_CTRL_NSEL(0) | CGU_PLL1_CTRL_NSEL(0)
| CGU_PLL1_CTRL_MSEL(16) | CGU_PLL1_CTRL_MSEL(16)
| CGU_PLL1_CTRL_FBSEL
| CGU_PLL1_CTRL_DIRECT; | CGU_PLL1_CTRL_DIRECT;
/* wait until stable */ /* wait until stable */