From 1723cd12a193df733afc82d83d219fe665d47b4f Mon Sep 17 00:00:00 2001 From: Jared Boone Date: Sat, 11 May 2013 12:25:54 -0700 Subject: [PATCH] Oops, read PLL1 documentation again. Looks like FBSEL=1 is for "normal operation". So include that, but use DIRECT=1 to skip the PSEL divider (which would prevent us producing 204MHz from an in-spec PLL frequency). --- firmware/common/hackrf_core.c | 1 + 1 file changed, 1 insertion(+) diff --git a/firmware/common/hackrf_core.c b/firmware/common/hackrf_core.c index 9f5806eb..12bd53c7 100644 --- a/firmware/common/hackrf_core.c +++ b/firmware/common/hackrf_core.c @@ -252,6 +252,7 @@ void cpu_clock_init(void) | CGU_PLL1_CTRL_PSEL(0) | CGU_PLL1_CTRL_NSEL(0) | CGU_PLL1_CTRL_MSEL(16) + | CGU_PLL1_CTRL_FBSEL | CGU_PLL1_CTRL_DIRECT; /* wait until stable */