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Merge branch 'master' of https://github.com/mossmann/hackrf

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This commit is contained in:
Jared Boone
2012-07-02 11:39:04 -07:00
parent 64656d1e92 130a15df37
commit 1098c3a712
21 changed files with 22257 additions and 835 deletions
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BIN
doc/SPIFI_Quad_Tests_OLS/SPIFI_QUAD_100MHZ_OLS_0_9_6b3_JellyBean_Startup_Dual4_M4_SPIFI_0.olp Normal file
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16106
doc/SPIFI_Quad_Tests_OLS/SPIFI_QUAD_100MHZ_OLS_0_9_6b3_JellyBean_Startup_Dual4_M4_SPIFI_0.ols Normal file
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127
doc/SPIFI_Quad_Tests_OLS/SPIFI_QUAD_100MHZ_OLS_0_9_6b3_JellyBean_Startup_Dual4_M4_SPIFI_0_Analyze.txt Normal file
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@ -0,0 +1,127 @@
OLS version used from: git://github.com/jawi/ols.git
Warning sometimes there's a bug between Mode3 & Mode0 in OLS 0.9.6b3
Expected is when /CS = 0 at first SCK Rising Edge data shall be read.
1) Read JDEC ID:
----------------
SPI Standard, Mode3, 8bits, MSB first, Show /CS & Honour /CS, SCK=About 32MHz:
Send(MOSI)=0x9F(Read JDEC ID)
Receive(MISO)=0xEF => Manufacturer ID(Winbond) and 0x40, 0x14 => Device ID
2) Read Status Register-2:
--------------------------
SPI Standard, Mode3, 8bits, MSB first, Show /CS & Honour /CS, SCK=About 32MHz:
Send(MOSI)=0x35(Read Status Register-2)
Receive(MISO)=0x02 (Status Register-2 => S15-S8)
3) Read Unknown Command 0xA3 (maybe for other SPIFI memory ??):
---------------------------------------------------------------
SPI Standard, Mode3, 8bits, MSB first, Show /CS & Honour /CS, SCK=About 32MHz:
Send(MOSI)=0xA3
Receive(MISO)=0x00 0x00 0x00
4) Fast Read Quad I/O with "Continuous Read Mode"(0xEB):
--------------------------------------------------------
SPI Standard, Mode3, 8bits, MSB first, Show /CS & Honour /CS, SCK=About 32MHz:
Send(MOSI)=0xEB(Fast Read Quad I/O)
SPI Quad, Mode3, 8bits, MSB first, Show /CS & Honour /CS:
Send(IO0 to IO3) hexa:
00 00 00 (A23-16) (A15-8) (A7-0)
A5 (M7-0) => A5 = 1010 0101 (Continuous Read Mode enabled)
A5 A5 (Dummy 2 bytes)
Receive(IO0 to IO3) hexa:
00 00 02 10 B1 01 00 14 (Data) => Vect Table = 0x10020000(Stack Pointer), 0x140001B1(Thumb) Real Addr=0x140001B0 (Reset_Handler/ResetISR)
79 01 00 14 7B 01 00 14 (Data)
7D 01 00 14 7F 01 00 14 (Data)
Dump from Debug (Big Endian to swap 32bits):
0x80000000 00000210 B1010014 79010014 7B010014 ....±...y...{...
0x80000010 7D010014 7F010014 }.......
5) Fast Read Quad I/O with "Continuous Read Mode"(0xEB):
--------------------------------------------------------
SPI Quad, Mode3, 8bits, MSB first, Show /CS & Honour /CS, SCK=About 32MHz:
Send(IO0 to IO3) hexa:
00 01 B0 (A23-16) (A15-8) (A7-0) (Corresponds to Real Addr=0x140001B0 (Reset_Handler/ResetISR))
A5 (M7-0) => A5 = 1010 0101 (Continuous Read Mode enabled)
A5 A5 (Dummy 2 bytes)
Receive(IO0 to IO3) hexa:
10 B5 72 B6 19 4B 1A 4A (Data)
1A 60 1A 4A 5A 60 1A 4A (Data)
4F F0 FF 33 13 60 53 60 (Data)
Dump from Debug (Big Endian to swap 32bits):
0x800001B0 10B572B6 194B1A4A 1A601A4A 5A601A4A .µr¶.K.J.`.JZ`.J
0x800001C0 4FF0FF33 13605360 Oðÿ3.`S`
6) Fast Read Quad I/O with "Continuous Read Mode"(0xEB):
--------------------------------------------------------
SPI Quad, Mode3, 8bits, MSB first, Show /CS & Honour /CS:
Send(IO0 to IO3) hexa:
00 02 18 (A23-16) (A15-8) (A7-0)
A5 (M7-0) => A5 = 1010 0101 (Continuous Read Mode enabled)
A5 A5 (Dummy 2 bytes)
Receive(IO0 to IO3) hexa:
FE E7 00 BF 00 31 05 40 (Data)
00 00 DF 10 FF F7 DF 01 (Data)
80 E2 00 E0 14 01 00 14 (Data)
Dump from Debug (Big Endian to swap 32bits):
0x80000218 FEE700BF 00310540 0000DF10 FFF7DF01 þç.¿.1.@..ß.ÿ÷ß.
0x80000228 80E200E0 14010014 .â.à....
7) Fast Read Quad I/O with "Continuous Read Mode"(0xEB):
--------------------------------------------------------
SPI Quad, Mode3, 8bits, MSB first, Show /CS & Honour /CS:
Send(IO0 to IO3) hexa:
00 01 C8 (A23-16) (A15-8) (A7-0)
A5 (M7-0) => A5 = 1010 0101 (Continuous Read Mode enabled)
A5 A5 (Dummy 2 bytes)
Receive(IO0 to IO3) hexa:
93 60 D3 60 13 61 53 61 (Data)
93 61 D3 61 62 B6 15 4C (Data)
Dump from Debug (Big Endian to swap 32bits):
0x800001C8 9360D360 13615361 9361D361 62B6154C .`Ó`.aSa.aÓab¶.L
8) Fast Read Quad I/O with "Continuous Read Mode"(0xEB):
--------------------------------------------------------
SPI Quad, Mode3, 8bits, MSB first, Show /CS & Honour /CS:
Send(IO0 to IO3) hexa:
00 02 30 (A23-16) (A15-8) (A7-0)
A5 (M7-0) => A5 = 1010 0101 (Continuous Read Mode enabled)
A5 A5 (Dummy 2 bytes)
Receive(IO0 to IO3) hexa:
50 01 00 14 78 01 00 14 (Data)
Dump from Debug (Big Endian to swap 32bits):
0x80000230 50010014 78010014 P...x...
9) Fast Read Quad I/O with "Continuous Read Mode"(0xEB):
--------------------------------------------------------
SPI Quad, Mode3, 8bits, MSB first, Show /CS & Honour /CS:
Send(IO0 to IO3) hexa:
00 01 D8 (A23-16) (A15-8) (A7-0)
A5 (M7-0) => A5 = 1010 0101 (Continuous Read Mode enabled)
A5 A5 (Dummy 2 bytes)
Receive(IO0 to IO3) hexa:
05 E0 20 68 61 68 A2 68 (Data)
0C 34 FF F7 D2 FF 12 4B (Data
9C 42 F6 D3 04 E0 20 68 (Data)
61 68 08 34 FF F7 D2 FF (Data)
0E 4B 9C 42 F7 D3 DF F8 (Data)
Dump from Debug (Big Endian to swap 32bits):
0x800001D8 05E02068 6168A268 0C34FFF7 D2FF124B .à hah¢h.4ÿ÷Òÿ.K
0x800001E8 9C42F6D3 04E02068 61680834 FFF7D2FF .BöÓ.à hah.4ÿ÷Òÿ
0x800001F8 0E4B9C42 F7D3DFF8 .K.B÷Óßø
Nota:
Tested on JellyBean.
SCK is about 32MHz After about 620us from startup.
SCK change to about 660KHz/700KHz during about 400us. (During Read from 00 0C 78 => During CGU SetPLL1 code).
SCK change from 4MHz to about 8MHz during about 15us. (Read from 00 0D 98 => During CGU SetPLL1 code).
SCK stabilize to 8MHz during 122us (no data anymore OLS memory is full) (Read from 00 05 B0).
...
During Code running the SCK run at 8MHz MCU is configured at 72MHz => 12MHz(IRC)*6.
SPIFI CLK(0x40050070) = 0xD000800 0x0D=IDIVB & 0x800=AUTOBLOCK_CLOCK_BIT Enabled
IDIVB_CTRL(0x4005004C) = 0x9000820 => IDIB=1000(8+1)=9 => for 72MHz Core => 72/9=8MHz
IDIVB_CTRL(0x4005004C) = 0x9000800 => IDIB=0000(0+1)=1 => for 72MHz Core => 72/1=72MHz => This configuration just crash.
IDIVB_CTRL(0x4005004C) = 0x9000800 => IDIB=0000(0+1)=1 => for 72MHz Core => 72/2=36MHz => This configuration works fine.

2
firmware/common/LPC4330_M4.ld
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@ -24,7 +24,7 @@
MEMORY
{
/* rom is really the shadow region that points to SPI flash or elsewhere */
rom (rx) : ORIGIN = 0x00000000, LENGTH = 1M
rom (rx) : ORIGIN = 0x14000000, LENGTH = 1M
ram (rwx) : ORIGIN = 0x10000000, LENGTH = 128K
/* there are some additional RAM regions */
}

28
firmware/simpletx/README
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@ -3,13 +3,21 @@ carrier.
Required Lemondrop -> Jellybean connections:
SCK: Lemondrop P3 pin 2 -> Jellybean P9 2
MOSI: Lemondrop P3 pin 4 -> Jellybean P9 4
MISO: Lemondrop P3 pin 6 -> Jellybean P9 6
SSEL: Lemondrop P3 pin 3 -> Jellybean P9 3
SCL: Lemondrop P7 pin 3 -> Jellybean P6 pin 3
SDA: Lemondrop P7 pin 5 -> Jellybean P6 pin 5
SDA: Lemondrop P7 pin 6 -> Jellybean P6 pin 6
VCC: Lemondrop P4 pin 2, 4, or 6 -> Jellybean P17 pin 2, 4, or 6
1V8: Lemondrop P11 pin 2, 4, or 6 -> Jellybean P16 pin 2, 4, or 6
GND: Lemondrop P5 -> Jellybean P13
SCK: Lemondrop P3 pin 2 -> Jellybean P9 2
CS_XCVR: Lemondrop P3 pin 3 -> Jellybean P9 3
MOSI: Lemondrop P3 pin 4 -> Jellybean P9 4
CS_AD: Lemondrop P3 pin 5 -> Jellybean P9 5
MISO: Lemondrop P3 pin 6 -> Jellybean P9 6
ENABLE: Lemondrop P6 pin 12 -> Jellybean P7 pin 12
RXENABLE: Lemondrop P6 pin 13 -> Jellybean P7 pin 13
TXENABLE: Lemondrop P6 pin 15 -> Jellybean P7 pin 15
SCL: Lemondrop P7 pin 3 -> Jellybean P6 pin 3
SDA: Lemondrop P7 pin 5 -> Jellybean P6 pin 5
SDA: Lemondrop P7 pin 6 -> Jellybean P6 pin 6
VCC: Lemondrop P4 pin 2, 4, or 6 -> Jellybean P17 pin 2, 4, or 6
GND: Lemondrop P5 -> Jellybean P13
For now we are running everything at 3.3 V, but in the future we may also
require:
1V8: Lemondrop P11 pin 2, 4, or 6 -> Jellybean P16 pin 2, 4, or 6

145
firmware/startup_systick/startup_systick.c
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@ -1,5 +1,5 @@
/*
* Copyright 2010 - 2012 Michael Ossmann
* Copyright 2012 Benjamin Vernoux
*
* This file is part of HackRF.
*
@ -64,7 +64,7 @@ void systick_setup(void)
g_ulSysTickCount = 0;
/* Disable IRQ globally */
asm volatile ("cpsid i");
__asm__("cpsid i");
/* Set processor Clock as Source Clock */
systick_set_clocksource(STK_CTRL_CLKSOURCE);
@ -90,7 +90,7 @@ void systick_setup(void)
nvic_set_priority(NVIC_SYSTICK_IRQ, 0xFF);
/* Enable IRQ globally */
asm volatile ("cpsie i");
__asm__("cpsie i");
}
void scs_dwt_cycle_counter_enabled(void)
@ -153,141 +153,6 @@ void sys_tick_handler(void)
g_ulSysTickCount++;
}
u32 test_nb_instruction_per_sec(void)
{
u32 start, end, wait_ms;
u32 tickms;
u32 nb_instructions_per_sec;
nb_instructions_per_sec = 0;
wait_ms = 1000;
start = sys_tick_get_time_ms();
do
{
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
nb_instructions_per_sec += 108;
end = sys_tick_get_time_ms();
tickms = sys_tick_delta_time_ms(start, end);
}while(tickms < wait_ms);
return nb_instructions_per_sec;
}
u32 nb_inst_per_sec0;
u32 nb_inst_per_sec1;
int main(void)
{
gpio_setup();
@ -300,10 +165,6 @@ int main(void)
systick_setup();
/* Test number of instruction per second */
nb_inst_per_sec0 = test_nb_instruction_per_sec();
nb_inst_per_sec1 = test_nb_instruction_per_sec();
gpio_set(PORT_LED1_3, (PIN_LED1|PIN_LED2|PIN_LED3)); /* LEDs on */
while (1)

10
firmware/startup_systick_perfo/Makefile Normal file
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@ -0,0 +1,10 @@
# Hey Emacs, this is a -*- makefile -*-
BINARY = startup_systick_perfo_SPIFI
SRC = startup_systick.c \
perf_mips.c \
../common/hackrf_core.c \
../common/si5351c.c
include ../common/Makefile_inc.mk

17
firmware/startup_systick_perfo/README Normal file
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@ -0,0 +1,17 @@
This program is an example of the startup sequence for HackRF (Jellybean with
Lemondrop attached).
Test number of instruction per second (MIPS) slow blink ON 1s, OFF 1s
Then after 16s (the 16tests) it blink LED1/2/3 ON/OFF each 250ms.
This example compute the number of instructions per second executed called also MIPS (Millions of Instructions Per Second)
This example code run from SPIFI (SPI Quad mode) and the tests check different loop size to compute the cache size used with SPIFI and estimated to less than 256Bytes (about 128 instructions in best case and in Thumb2).
See result_exec_from_SPIFI.txt for more details.
Required Lemondrop -> Jellybean connections:
SCL: Lemondrop P7 pin 3 -> Jellybean P6 pin 3
SDA: Lemondrop P7 pin 5 -> Jellybean P6 pin 5
SDA: Lemondrop P7 pin 6 -> Jellybean P6 pin 6
VCC: Lemondrop P4 pin 2, 4, or 6 -> Jellybean P17 pin 2, 4, or 6
1V8: Lemondrop P11 pin 2, 4, or 6 -> Jellybean P16 pin 2, 4, or 6
GND: Lemondrop P5 -> Jellybean P13

2220
firmware/startup_systick_perfo/perf_mips.c Normal file
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File diff suppressed because it is too large Load Diff

33
firmware/startup_systick_perfo/result_exec_from_SPIFI.txt Normal file
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@ -0,0 +1,33 @@
Frequency MCU Core M4 = 204MHz
"nb_inst_per_sec" 0x10000008
nb_inst_per_sec[0] 195609816 test_nb_instruction_per_sec_100_nop_asm();
nb_inst_per_sec[1] 195577462 test_nb_instruction_per_sec_105_nop_asm();
nb_inst_per_sec[2] 195525410 test_nb_instruction_per_sec_110_nop_asm();
nb_inst_per_sec[3] 35423508 test_nb_instruction_per_sec_115_nop_asm();
nb_inst_per_sec[4] 5058688 test_nb_instruction_per_sec_120_nop_asm();
nb_inst_per_sec[5] 5094868 test_nb_instruction_per_sec_150_nop_asm();
nb_inst_per_sec[6] 5162144 test_nb_instruction_per_sec_200_nop_asm();
nb_inst_per_sec[7] 5505696 test_nb_instruction_per_sec_1000_nop_asm();
nb_inst_per_sec[8] 195600420 test_nb_instruction_per_sec_100_nop_asm();
nb_inst_per_sec[9] 195578027 test_nb_instruction_per_sec_105_nop_asm();
nb_inst_per_sec[10] 195525882 test_nb_instruction_per_sec_110_nop_asm();
nb_inst_per_sec[11] 35422647 test_nb_instruction_per_sec_115_nop_asm();
nb_inst_per_sec[12] 5058688 test_nb_instruction_per_sec_120_nop_asm();
nb_inst_per_sec[13] 5094868 test_nb_instruction_per_sec_150_nop_asm();
nb_inst_per_sec[14] 5162144 test_nb_instruction_per_sec_200_nop_asm();
nb_inst_per_sec[15] 5505696 test_nb_instruction_per_sec_1000_nop_asm();
Real speed expected from SPIFI without cache (with lot of nop)
Oscilloscope Freq SPIFI SCK = 22.50MHz to 22.83MHz (in reality 22.67MHz => 204/9 => SPIFI_CLK connected to IDIVB & IDIVB default=9)
So worst case 22.50Mbits*4 = 90Mbits/s => 11.25MBytes/s with an overhead of about 50% due to SPIFI protocol addr ... => 5.625MB
1 nop = 2 bytes (THUMB 0x00 0xBF) => Max 5.625 Millions instruction per second
110 NOP is in fact 110 + 9 (including loop overhead)
119*2 = 238 bytes
115NOP + 9 => does not enter in cache !! (248bytes)
Internal Cache size is about 256Bytes maybe shared Code/Data.
SPIFI obtained min=5.05 MIPS, max=195.6 MIPS

190
firmware/startup_systick_rom_to_ram/startup_systick.c → firmware/startup_systick_perfo/startup_systick.c
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@ -64,7 +64,7 @@ void systick_setup(void)
g_ulSysTickCount = 0;
/* Disable IRQ globally */
asm volatile ("cpsid i");
__asm__("cpsid i");
/* Set processor Clock as Source Clock */
systick_set_clocksource(STK_CTRL_CLKSOURCE);
@ -90,7 +90,7 @@ void systick_setup(void)
nvic_set_priority(NVIC_SYSTICK_IRQ, 0xFF);
/* Enable IRQ globally */
asm volatile ("cpsie i");
__asm__("cpsie i");
}
void scs_dwt_cycle_counter_enabled(void)
@ -153,140 +153,18 @@ void sys_tick_handler(void)
g_ulSysTickCount++;
}
u32 test_nb_instruction_per_sec(void)
{
u32 start, end, wait_ms;
u32 tickms;
u32 nb_instructions_per_sec;
u32 nb_inst_per_sec[16];
nb_instructions_per_sec = 0;
wait_ms = 1000;
extern u32 test_nb_instruction_per_sec_100_nop_asm();
extern u32 test_nb_instruction_per_sec_105_nop_asm();
extern u32 test_nb_instruction_per_sec_110_nop_asm();
extern u32 test_nb_instruction_per_sec_115_nop_asm();
extern u32 test_nb_instruction_per_sec_120_nop_asm();
extern u32 test_nb_instruction_per_sec_150_nop_asm();
extern u32 test_nb_instruction_per_sec_200_nop_asm();
extern u32 test_nb_instruction_per_sec_1000_nop_asm();
start = sys_tick_get_time_ms();
do
{
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
asm volatile ("nop ");
nb_instructions_per_sec += 100;
end = sys_tick_get_time_ms();
tickms = sys_tick_delta_time_ms(start, end);
}while(tickms < wait_ms);
return nb_instructions_per_sec;
}
u32 nb_inst_per_sec0;
u32 nb_inst_per_sec1;
#define LED1_TOGGLE() (gpio_toggle(PORT_LED1_3, (PIN_LED1)))
int main(void)
{
@ -300,25 +178,57 @@ int main(void)
systick_setup();
/* Test number of instruction per second */
nb_inst_per_sec0 = test_nb_instruction_per_sec();
nb_inst_per_sec1 = test_nb_instruction_per_sec();
gpio_clear(PORT_LED1_3, (PIN_LED1)); /* LED1 off */
gpio_set(PORT_LED1_3, (PIN_LED1|PIN_LED2|PIN_LED3)); /* LEDs on */
/* Test number of instruction per second (MIPS) slow blink ON 1s, OFF 1s */
LED1_TOGGLE();
nb_inst_per_sec[0] = test_nb_instruction_per_sec_100_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[1]= test_nb_instruction_per_sec_105_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[2]= test_nb_instruction_per_sec_110_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[3]= test_nb_instruction_per_sec_115_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[4] = test_nb_instruction_per_sec_120_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[5] = test_nb_instruction_per_sec_150_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[6] = test_nb_instruction_per_sec_200_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[7] = test_nb_instruction_per_sec_1000_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[8] = test_nb_instruction_per_sec_100_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[9]= test_nb_instruction_per_sec_105_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[10]= test_nb_instruction_per_sec_110_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[11]= test_nb_instruction_per_sec_115_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[12] = test_nb_instruction_per_sec_120_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[13] = test_nb_instruction_per_sec_150_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[14] = test_nb_instruction_per_sec_200_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[15] = test_nb_instruction_per_sec_1000_nop_asm();
LED1_TOGGLE();
/* Test finished fast blink */
while (1)
{
gpio_set(PORT_LED1_3, (PIN_LED1)); /* LED1 on */
gpio_set(PORT_LED1_3, (PIN_LED2)); /* LED2 on */
gpio_set(PORT_LED1_3, (PIN_LED3)); /* LED3 on */
sys_tick_wait_time_ms(500);
sys_tick_wait_time_ms(250);
gpio_clear(PORT_LED1_3, (PIN_LED3)); /* LED3 off */
gpio_clear(PORT_LED1_3, (PIN_LED2)); /* LED2 off */
gpio_clear(PORT_LED1_3, (PIN_LED1)); /* LED1 off */
sys_tick_wait_time_ms(500);
sys_tick_wait_time_ms(250);
}
return 0;

5
firmware/startup_systick_rom_to_ram/Makefile → firmware/startup_systick_perfo_rom_to_ram/Makefile
View File

@ -1,8 +1,9 @@
# Hey Emacs, this is a -*- makefile -*-
BINARY = startup_systick
BINARY = startup_systick_perfo_rom_to_ram
SRC = $(BINARY).c \
SRC = startup_systick.c \
perf_mips.c \
../common/hackrf_core.c \
../common/si5351c.c

7
firmware/startup_systick_rom_to_ram/README → firmware/startup_systick_perfo_rom_to_ram/README
View File

@ -1,6 +1,11 @@
This program is an example of the startup sequence for HackRF (Jellybean with
Lemondrop attached).
LED1, LED2, and LED3 are blinking at exactly a frequency of 1Hz upon success.
Test number of instruction per second (MIPS) slow blink ON 1s, OFF 1s
Then after 16s (the 16tests) it blink LED1/2/3 ON/OFF each 250ms.
This example compute the number of instructions per second executed called also MIPS (Millions of Instructions Per Second)
This example code run from SRAM so maximum performance expected is 204MIPS.
See result details in result_exec_from_SRAM.txt
Required Lemondrop -> Jellybean connections:

2220
firmware/startup_systick_perfo_rom_to_ram/perf_mips.c Normal file
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File diff suppressed because it is too large Load Diff

22
firmware/startup_systick_perfo_rom_to_ram/result_exec_from_SRAM.txt Normal file
View File

@ -0,0 +1,22 @@
Frequency MCU Core M4 = 204MHz
"nb_inst_per_sec" 0x10080008
nb_inst_per_sec[0] 202091544 test_nb_instruction_per_sec_100_nop_asm();
nb_inst_per_sec[1] 202172820 test_nb_instruction_per_sec_105_nop_asm();
nb_inst_per_sec[2] 202247988 test_nb_instruction_per_sec_110_nop_asm();
nb_inst_per_sec[3] 202317165 test_nb_instruction_per_sec_115_nop_asm();
nb_inst_per_sec[4] 202381696 test_nb_instruction_per_sec_120_nop_asm();
nb_inst_per_sec[5] 202680030 test_nb_instruction_per_sec_150_nop_asm();
nb_inst_per_sec[6] 202986160 test_nb_instruction_per_sec_200_nop_asm();
nb_inst_per_sec[7] 203760144 test_nb_instruction_per_sec_1000_nop_asm();
nb_inst_per_sec[8] 202091220 test_nb_instruction_per_sec_100_nop_asm();
nb_inst_per_sec[9] 202172820 test_nb_instruction_per_sec_105_nop_asm();
nb_inst_per_sec[10] 202247988 test_nb_instruction_per_sec_110_nop_asm();
nb_inst_per_sec[11] 202317165 test_nb_instruction_per_sec_115_nop_asm();
nb_inst_per_sec[12] 202381696 test_nb_instruction_per_sec_120_nop_asm();
nb_inst_per_sec[13] 202680030 test_nb_instruction_per_sec_150_nop_asm();
nb_inst_per_sec[14] 202986160 test_nb_instruction_per_sec_200_nop_asm();
nb_inst_per_sec[15] 203760144 test_nb_instruction_per_sec_1000_nop_asm();
SRAM execution, expected 204 MIPS best case obtained min=202 MIPS, max=203.7 MIPS

235
firmware/startup_systick_perfo_rom_to_ram/startup_systick.c Normal file
View File

@ -0,0 +1,235 @@
/*
* Copyright 2010 - 2012 Michael Ossmann
*
* This file is part of HackRF.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 51 Franklin Street,
* Boston, MA 02110-1301, USA.
*/
#include <libopencm3/lpc43xx/gpio.h>
#include <libopencm3/lpc43xx/scu.h>
#include <libopencm3/lpc43xx/i2c.h>
#include <libopencm3/lpc43xx/nvic.h>
#include <libopencm3/lpc43xx/systick.h>
#include <libopencm3/cm3/scs.h>
#include "hackrf_core.h"
/* Global counter incremented by SysTick Interrupt each millisecond */
volatile u32 g_ulSysTickCount;
u32 g_NbCyclePerSecond;
void gpio_setup(void)
{
/* Configure SCU Pin Mux as GPIO */
scu_pinmux(SCU_PINMUX_LED1, SCU_GPIO_FAST);
scu_pinmux(SCU_PINMUX_LED2, SCU_GPIO_FAST);
scu_pinmux(SCU_PINMUX_LED3, SCU_GPIO_FAST);
scu_pinmux(SCU_PINMUX_EN1V8, SCU_GPIO_FAST);
/* Configure all GPIO as Input (safe state) */
GPIO0_DIR = 0;
GPIO1_DIR = 0;
GPIO2_DIR = 0;
GPIO3_DIR = 0;
GPIO4_DIR = 0;
GPIO5_DIR = 0;
GPIO6_DIR = 0;
GPIO7_DIR = 0;
/* Configure GPIO2[1/2/8] (P4_1/2 P6_12) as output. */
GPIO2_DIR |= (PIN_LED1|PIN_LED2|PIN_LED3);
/* GPIO3[6] on P6_10 as output. */
GPIO3_DIR |= PIN_EN1V8;
}
void systick_setup(void)
{
u32 systick_reload_val;
g_ulSysTickCount = 0;
/* Disable IRQ globally */
__asm__("cpsid i");
/* Set processor Clock as Source Clock */
systick_set_clocksource(STK_CTRL_CLKSOURCE);
/* Get SysTick calibration value to obtain by default 1 tick = 10ms */
systick_reload_val = systick_get_calib();
/*
* Calibration seems wrong on LPC43xx(TBC) for default Freq it assume System Clock is 12MHz but it is 12*17=204MHz
* Fix the Calibration value bu multiplication by 17
*/
systick_reload_val = (systick_reload_val*17);
/* To obtain 1ms per tick just divide by 10 the 10ms base tick and set the reload */
systick_reload_val = systick_reload_val/10;
systick_set_reload(systick_reload_val);
systick_interrupt_enable();
/* Start counting. */
systick_counter_enable();
/* Set SysTick Priority to maximum */
nvic_set_priority(NVIC_SYSTICK_IRQ, 0xFF);
/* Enable IRQ globally */
__asm__("cpsie i");
}
void scs_dwt_cycle_counter_enabled(void)
{
SCS_DEMCR |= SCS_DEMCR_TRCENA;
SCS_DWT_CTRL |= SCS_DWT_CTRL_CYCCNTENA;
}
u32 sys_tick_get_time_ms(void)
{
return g_ulSysTickCount;
}
u32 sys_tick_delta_time_ms(u32 start, u32 end)
{
#define MAX_T_U32 ((2^32)-1)
u32 diff;
if(end > start)
{
diff=end-start;
}else
{
diff=MAX_T_U32-(start-end)+1;
}
return diff;
}
void sys_tick_wait_time_ms(u32 wait_ms)
{
u32 start, end;
u32 tickms;
start = sys_tick_get_time_ms();
do
{
end = sys_tick_get_time_ms();
tickms = sys_tick_delta_time_ms(start, end);
}while(tickms < wait_ms);
}
/* Called each 1ms/1000Hz by interrupt
1) Count the number of cycle per second.
2) Increment g_ulSysTickCount counter.
*/
void sys_tick_handler(void)
{
if(g_ulSysTickCount==0)
{
/* Clear Cycle Counter*/
SCS_DWT_CYCCNT = 0;
}else if(g_ulSysTickCount==1000)
{
/* Capture number of cycle elapsed during 1 second */
g_NbCyclePerSecond = SCS_DWT_CYCCNT;
}
g_ulSysTickCount++;
}
u32 nb_inst_per_sec[16];
extern u32 test_nb_instruction_per_sec_100_nop_asm();
extern u32 test_nb_instruction_per_sec_105_nop_asm();
extern u32 test_nb_instruction_per_sec_110_nop_asm();
extern u32 test_nb_instruction_per_sec_115_nop_asm();
extern u32 test_nb_instruction_per_sec_120_nop_asm();
extern u32 test_nb_instruction_per_sec_150_nop_asm();
extern u32 test_nb_instruction_per_sec_200_nop_asm();
extern u32 test_nb_instruction_per_sec_1000_nop_asm();
#define LED1_TOGGLE() (gpio_toggle(PORT_LED1_3, (PIN_LED1)))
int main(void)
{
gpio_setup();
gpio_set(PORT_EN1V8, PIN_EN1V8); /* 1V8 on */
cpu_clock_init();
scs_dwt_cycle_counter_enabled();
systick_setup();
gpio_clear(PORT_LED1_3, (PIN_LED1)); /* LED1 off */
/* Test number of instruction per second (MIPS) slow blink ON 1s, OFF 1s */
LED1_TOGGLE();
nb_inst_per_sec[0] = test_nb_instruction_per_sec_100_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[1]= test_nb_instruction_per_sec_105_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[2]= test_nb_instruction_per_sec_110_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[3]= test_nb_instruction_per_sec_115_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[4] = test_nb_instruction_per_sec_120_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[5] = test_nb_instruction_per_sec_150_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[6] = test_nb_instruction_per_sec_200_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[7] = test_nb_instruction_per_sec_1000_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[8] = test_nb_instruction_per_sec_100_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[9]= test_nb_instruction_per_sec_105_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[10]= test_nb_instruction_per_sec_110_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[11]= test_nb_instruction_per_sec_115_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[12] = test_nb_instruction_per_sec_120_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[13] = test_nb_instruction_per_sec_150_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[14] = test_nb_instruction_per_sec_200_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[15] = test_nb_instruction_per_sec_1000_nop_asm();
LED1_TOGGLE();
/* Test finished fast blink */
while (1)
{
gpio_set(PORT_LED1_3, (PIN_LED1)); /* LED1 on */
gpio_set(PORT_LED1_3, (PIN_LED2)); /* LED2 on */
gpio_set(PORT_LED1_3, (PIN_LED3)); /* LED3 on */
sys_tick_wait_time_ms(250);
gpio_clear(PORT_LED1_3, (PIN_LED3)); /* LED3 off */
gpio_clear(PORT_LED1_3, (PIN_LED2)); /* LED2 off */
gpio_clear(PORT_LED1_3, (PIN_LED1)); /* LED1 off */
sys_tick_wait_time_ms(250);
}
return 0;
}

70
hardware/bubblegum/bubblegum-cache.lib
View File

@ -1,4 +1,4 @@
EESchema-LIBRARY Version 2.3 Date: Thu Jun 21 12:06:12 2012
EESchema-LIBRARY Version 2.3 Date: Sun Jul 1 15:21:04 2012
#encoding utf-8
#
# BALUN
@ -83,6 +83,22 @@ X ~ 10 400 -200 300 L 60 60 1 1 P I
ENDDRAW
ENDDEF
#
# DMC2400
#
DEF DMC2400 U 0 40 Y Y 1 F N
F0 "U" -50 0 60 V V C CNN
F1 "DMC2400" 50 0 60 V V C CNN
DRAW
S -250 250 250 -250 0 1 0 N
X S1 1 -400 100 150 R 50 50 1 1 B
X G1 2 -400 0 150 R 50 50 1 1 I
X D2 3 -400 -100 150 R 50 50 1 1 B
X S2 4 400 -100 150 L 50 50 1 1 B
X G2 5 400 0 150 L 50 50 1 1 I
X D1 6 400 100 150 L 50 50 1 1 B
ENDDRAW
ENDDEF
#
# FIL-DEA
#
DEF FIL-DEA U 0 40 Y Y 1 F N
@ -104,10 +120,10 @@ F0 "U" 0 50 60 H V C CNN
F1 "FIL-LP0603" 0 -50 60 H V C CNN
DRAW
S -300 200 300 -200 0 1 0 N
X IN 1 600 150 300 L 50 50 1 1 B
X OUT 2 -600 150 300 R 50 50 1 1 B
X GND 3 -600 -150 300 R 50 50 1 1 W
X GND 4 600 -150 300 L 50 50 1 1 W
X OUT 1 -600 150 300 R 50 50 1 1 B
X GND 2 -600 -150 300 R 50 50 1 1 W
X GND 3 600 -150 300 L 50 50 1 1 W
X IN 4 600 150 300 L 50 50 1 1 B
ENDDRAW
ENDDEF
#
@ -197,42 +213,18 @@ X 2 2 0 -300 100 U 70 70 1 1 P
ENDDRAW
ENDDEF
#
# MOS_N
# NCP699
#
DEF MOS_N Q 0 0 N Y 1 F N
F0 "Q" 10 170 60 H V R CNN
F1 "MOS_N" 10 -150 60 H V R CNN
ALIAS MOSFET_N
DEF NCP699 U 0 40 Y Y 1 F N
F0 "U" 0 200 60 H V C CNN
F1 "NCP699" 0 -200 60 H V C CNN
DRAW
P 2 0 1 8 -50 -100 -50 100 N
P 2 0 1 10 0 -150 0 150 N
P 2 0 1 0 100 -100 0 -100 N
P 2 0 1 0 100 100 0 100 N
P 3 0 1 8 100 -100 100 0 50 0 N
P 5 0 1 8 50 30 50 -30 0 0 50 30 50 30 N
X D D 100 200 100 D 40 40 1 1 P
X G G -200 0 150 R 40 40 1 1 I
X S S 100 -200 100 U 40 40 1 1 P
ENDDRAW
ENDDEF
#
# MOS_P
#
DEF MOS_P Q 0 40 Y N 1 F N
F0 "Q" 0 190 60 H V R CNN
F1 "MOS_P" 0 -180 60 H V R CNN
ALIAS MOSFET_P
DRAW
P 2 0 1 8 -50 -100 -50 100 N
P 2 0 1 10 0 -150 0 150 N
P 2 0 1 8 30 0 0 0 N
P 2 0 1 0 100 -100 0 -100 N
P 2 0 1 0 100 100 0 100 N
P 3 0 1 0 80 0 100 0 100 -100 N
P 5 0 1 8 30 40 30 -30 80 0 30 40 30 40 N
X D D 100 200 100 D 40 40 1 1 P
X G G -200 0 150 R 40 40 1 1 I
X S S 100 -200 100 U 40 40 1 1 P
S -250 250 250 -250 0 1 0 N
X VIN 1 -400 100 150 R 50 50 1 1 W
X GND 2 -400 0 150 R 50 50 1 1 W
X EN 3 -400 -100 150 R 50 50 1 1 I
X NC 4 400 -100 150 L 50 50 1 1 N
X VOUT 5 400 100 150 L 50 50 1 1 w
ENDDRAW
ENDDEF
#

1604
hardware/bubblegum/bubblegum.sch
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File diff suppressed because it is too large Load Diff

2
hardware/kicad/hackrf.dcm
View File

@ -1,4 +1,4 @@
EESchema-DOCLIB Version 2.0 Date: Thu Jun 21 18:14:36 2012
EESchema-DOCLIB Version 2.0 Date: Sun Jul 1 11:50:49 2012
#
$CMP GSG-DIODE-TVS-BI
D Diode zener

33
hardware/kicad/hackrf.lib
View File

@ -1,4 +1,4 @@
EESchema-LIBRARY Version 2.3 Date: Thu Jun 21 18:14:36 2012
EESchema-LIBRARY Version 2.3 Date: Sun Jul 1 11:50:49 2012
#encoding utf-8
#
# BALUN
@ -120,6 +120,22 @@ X P29 29 -400 -650 300 R 60 30 1 1 P I
ENDDRAW
ENDDEF
#
# DMC2400
#
DEF DMC2400 U 0 40 Y Y 1 F N
F0 "U" -50 0 60 V V C CNN
F1 "DMC2400" 50 0 60 V V C CNN
DRAW
S -250 250 250 -250 0 1 0 N
X S1 1 -400 100 150 R 50 50 1 1 B
X G1 2 -400 0 150 R 50 50 1 1 I
X D2 3 -400 -100 150 R 50 50 1 1 B
X S2 4 400 -100 150 L 50 50 1 1 B
X G2 5 400 0 150 L 50 50 1 1 I
X D1 6 400 100 150 L 50 50 1 1 B
ENDDRAW
ENDDEF
#
# FIL-DEA
#
DEF FIL-DEA U 0 40 Y Y 1 F N
@ -662,6 +678,21 @@ X VDD 39 350 1200 300 D 50 50 1 1 W
ENDDRAW
ENDDEF
#
# NCP699
#
DEF NCP699 U 0 40 Y Y 1 F N
F0 "U" 0 200 60 H V C CNN
F1 "NCP699" 0 -200 60 H V C CNN
DRAW
S -250 250 250 -250 0 1 0 N
X VIN 1 -400 100 150 R 50 50 1 1 W
X GND 2 -400 0 150 R 50 50 1 1 W
X EN 3 -400 -100 150 R 50 50 1 1 I
X NC 4 400 -100 150 L 50 50 1 1 N
X VOUT 5 400 100 150 L 50 50 1 1 w
ENDDRAW
ENDDEF
#
# PE4140
#
DEF PE4140 U 0 40 Y Y 1 F N

16
hardware/lollipop/lollipop.brd
View File

@ -1,4 +1,4 @@
PCBNEW-BOARD Version 1 date Thu Jun 21 19:11:32 2012
PCBNEW-BOARD Version 1 date Sat Jun 23 08:15:06 2012
# Created by Pcbnew(2011-06-30 BZR 3033)-stable
@ -10,7 +10,7 @@ EnabledLayers 1FFF8007
Links 383
NoConn 53
Di 20440 8924 38560 29076
Ndraw 12
Ndraw 14
Ntrack 1423
Nzone 0
BoardThickness 630
@ -21,7 +21,7 @@ $EndGENERAL
$SHEETDESCR
Sheet User 6000 4000
Title ""
Date "22 jun 2012"
Date "23 jun 2012"
Rev ""
Comp ""
Comment1 ""
@ -6858,6 +6858,16 @@ Le -1954803976
$EndPAD
$EndMODULE GSG-LP0603
$TEXTPCB
Te "23 Jun 2012"
Po 28250 20890 600 800 120 0
De 21 1 0 Normal
$EndTEXTPCB
$TEXTPCB
Te "lollipop"
Po 30980 22870 600 800 120 0
De 21 1 0 Normal
$EndTEXTPCB
$TEXTPCB
Te "TX-in"
Po 37000 16250 300 400 75 0
De 21 1 0 Normal