f8b6e9145c
HOST_SYNC is only connected to connector P28, and is therefore not driven (left to float) unless connected to some synchronization signal. Pull it up to keep it steady. In doing so, I had to switch all unused pins to pull-up, and all input-only and tri-state pins to float. All input/tri-state pins except for HOST_SYNC are tied to the microcontroller and can be pulled up there.
CPLD interface between LPC43xx microcontroller SGPIO peripheral and MAX5864 RF codec.
CPLD-based triggered capture
To build this VHDL project and produce an SVF file for flashing the CPLD:
- Xilinx WebPACK 13.4 for Windows or Linux.
Generate an XSVF
After generating a programming file:
- In the ISE Project Navigator, "Processes: top - Behavioral" pane, double-click "Configure Target Device".
- Click "OK" to open iMPACT.
- Ctrl-N to create a "New Project".
- "Yes" to automatically create and save a project file.
- Select "Prepare a Boundary-Scan File", choose "XSVF".
- Select file name "default.xsvf".
- Click "OK" to start adding devices.
- Assign new configuration file: "top.jed".
- Right-click the "xc2c64a top.jed" icon and select "Erase". Accept defaults.
- Right-click the "xc2c64a top.jed" icon and select "Program".
- Right-click the "xc2c64a top.jed" icon and select "Verify".
- Choose menu "Output" -> "XSVF File" -> "Stop Writing to XSVF File".
- Close iMPACT.
To Program
$ hackrf_cpldjtag -x default.xsvf