f08e0c17bf
This commit is separate from the previous one which adds the macros, in order to make the diffs easier to read.
421 lines
20 KiB
ArmAsm
421 lines
20 KiB
ArmAsm
/*
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* Copyright 2019-2022 Great Scott Gadgets
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*
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* This file is part of HackRF.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 51 Franklin Street,
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* Boston, MA 02110-1301, USA.
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*/
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/*
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Introduction
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============
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This file contains the code that runs on the Cortex-M0 core of the LPC43xx.
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The M0 core is used to implement all the timing-critical usage of the SGPIO
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peripheral, which interfaces to the MAX5864 ADC/DAC via the CPLD.
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The M0 reads or writes 32 bytes at a time from the SGPIO registers,
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transferring these bytes to or from a shared USB bulk buffer. The M4 core
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handles transferring data between this buffer and the USB host.
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The SGPIO peripheral is set up and enabled by the M4 core. All the M0 needs to
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do is handle the SGPIO exchange interrupt, which indicates that new data can
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now be read from or written to the SGPIO shadow registers.
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Timing
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======
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This code has tight timing constraints.
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We have to complete a read or write from SGPIO every 163 cycles.
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The CPU clock is 204MHz. We exchange 32 bytes at a time in the SGPIO
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registers, which is 16 samples worth of IQ data. At the maximum sample rate of
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20MHz, the SGPIO update rate is 20 / 16 = 1.25MHz. So we have 204 / 1.25 =
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163.2 cycles available.
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Access to the SGPIO peripheral is slow, due to the asynchronous bridge that
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connects it to the AHB bus matrix. Section 20.4.1 of the LPC43xx user manual
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(UM10503) specifies the access latencies as:
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Read: 4 x MCLK + 4 x CLK_PERIPH_SGPIO
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Write: 4 x MCLK + 2 x CLK_PERIPH_SGPIO
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In our case both these clocks are at 204MHz so reads add 8 cycles and writes
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add 6. These are latencies that add to the usual M0 instruction timings, so an
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ldr from SGPIO takes 10 cycles, and an str to SGPIO takes 8 cycles.
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These latencies are assumed to apply to all accesses to the SGPIO peripheral's
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address space, which includes its interrupt control registers as well as the
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shadow registers.
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There are four key code paths, with the following worst-case timings:
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RX, normal: 147 cycles
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RX, overrun: 76 cycles
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TX, normal: 138 cycles
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TX, underrun: 142 cycles
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Design
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======
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Due to the timing constraints, this code is highly optimised.
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This is the only code that runs on the M0, so it does not need to follow
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calling conventions, nor use features of the architecture in standard ways.
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The SGPIO handling does not run as an ISR. It polls the interrupt status.
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This saves the cycle costs of interrupt entry and exit, and allows all
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registers to be used freely.
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All possible registers, including the stack pointer and link register, can be
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used to store values needed in the code, to minimise memory loads and stores.
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There are no function calls. There is no stack usage. All values are in
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registers and fixed memory addresses.
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*/
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// Constants that point to registers we'll need to modify in the SGPIO block.
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.equ SGPIO_SHADOW_REGISTERS_BASE, 0x40101100
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.equ SGPIO_EXCHANGE_INTERRUPT_BASE, 0x40101F00
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// Offsets into the interrupt control registers.
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.equ INT_CLEAR, 0x30
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.equ INT_STATUS, 0x2C
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// Buffer that we're funneling data to/from.
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.equ TARGET_DATA_BUFFER, 0x20008000
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.equ TARGET_BUFFER_SIZE, 0x8000
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.equ TARGET_BUFFER_MASK, 0x7fff
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// Base address of the state structure.
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.equ STATE_BASE, 0x20007000
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// Offsets into the state structure.
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.equ MODE, 0x00
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.equ M0_COUNT, 0x04
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.equ M4_COUNT, 0x08
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.equ NUM_SHORTFALLS, 0x0C
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.equ LONGEST_SHORTFALL, 0x10
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.equ SHORTFALL_LIMIT, 0x14
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// Operating modes.
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.equ MODE_IDLE, 0
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.equ MODE_RX, 1
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.equ MODE_TX_START, 2
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.equ MODE_TX_RUN, 3
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// Our slice chain is set up as follows (ascending data age; arrows are reversed for flow):
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// L -> F -> K -> C -> J -> E -> I -> A
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// Which has equivalent shadow register offsets:
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// 44 -> 20 -> 40 -> 8 -> 36 -> 16 -> 32 -> 0
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.equ SLICE0, 44
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.equ SLICE1, 20
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.equ SLICE2, 40
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.equ SLICE3, 8
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.equ SLICE4, 36
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.equ SLICE5, 16
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.equ SLICE6, 32
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.equ SLICE7, 0
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/* Allocations of single-use registers */
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buf_size_minus_32 .req r14
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state .req r13
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buf_base .req r12
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buf_mask .req r11
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shortfall_length .req r10
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hi_zero .req r9
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sgpio_data .req r7
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sgpio_int .req r6
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count .req r5
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buf_ptr .req r4
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/* Macros */
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.macro reset_counts
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// Reset counts.
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//
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// Clobbers:
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zero .req r0
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mov zero, #0 // zero = 0 // 1
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str zero, [state, #M0_COUNT] // state.m0_count = zero // 2
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str zero, [state, #M4_COUNT] // state.m4_count = zero // 2
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str zero, [state, #NUM_SHORTFALLS] // state.num_shortfalls = zero // 2
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str zero, [state, #LONGEST_SHORTFALL] // state.longest_shortfall = zero // 2
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mov shortfall_length, zero // shortfall_length = zero // 1
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.endm
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.macro await_sgpio
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// Wait for, then clear, SGPIO exchange interrupt flag.
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//
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// Clobbers:
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int_status .req r0
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scratch .req r1
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// The worst case timing is assumed to occur when reading the interrupt
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// status register *just* misses the flag being set - so we include the
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// cycles required to check it a second time.
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//
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// We also assume that we can spend a full 10 cycles doing an ldr from
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// SGPIO the first time (2 for ldr, plus 8 for SGPIO-AHB bus latency),
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// and still miss a flag that was set at the start of those 10 cycles.
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//
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// This latter asssumption is probably slightly pessimistic, since the
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// sampling of the flag on the SGPIO side must occur some time after
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// the ldr instruction begins executing on the M0. However, we avoid
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// relying on any assumptions about the timing details of a read over
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// the SGPIO to AHB bridge.
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int_wait:
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// Spin on the exchange interrupt status, shifting the slice A flag to the carry flag.
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ldr int_status, [sgpio_int, #INT_STATUS] // int_status = SGPIO_STATUS_1 // 10, twice
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lsr scratch, int_status, #1 // scratch = int_status >> 1 // 1, twice
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bcc int_wait // if !carry: goto int_wait // 3, then 1
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// Clear the interrupt pending bits that were set.
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str int_status, [sgpio_int, #INT_CLEAR] // SGPIO_CLR_STATUS_1 = int_status // 8
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.endm
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.macro update_buf_ptr
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// Update the address of the buffer segment we want to write to / read from.
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ldr count, [state, #M0_COUNT] // count = state.m0_count // 2
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mov buf_ptr, buf_mask // buf_ptr = buf_mask // 1
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and buf_ptr, count // buf_ptr &= count // 1
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add buf_ptr, buf_base // buf_ptr += buf_base // 1
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.endm
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.macro update_counts
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// Update counts after successful SGPIO operation.
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// Update the byte count and store the new value.
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add count, #32 // count += 32 // 1
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str count, [state, #M0_COUNT] // state.m0_count = count // 2
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// We didn't have a shortfall, so the current shortfall length is zero.
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mov shortfall_length, hi_zero // shortfall_length = hi_zero // 1
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.endm
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.macro handle_shortfall
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// Handle a shortfall.
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//
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// Clobbers:
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length .req r0
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num .req r1
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longest .req r1
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limit .req r1
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// Get current shortfall length from high register.
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mov length, shortfall_length // length = shortfall_length // 1
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// Is this a new shortfall?
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cmp length, #0 // if length > 0: // 1
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bgt extend_shortfall // goto extend_shortfall // 1 thru, 3 taken
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// If so, increase the shortfall count.
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ldr num, [state, #NUM_SHORTFALLS] // num = state.num_shortfalls // 2
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add num, #1 // num += 1 // 1
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str num, [state, #NUM_SHORTFALLS] // state.num_shortfalls = num // 2
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extend_shortfall:
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// Extend the length of the current shortfall, and store back in high register.
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add length, #32 // length += 32 // 1
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mov shortfall_length, length // shortfall_length = length // 1
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// Is this now the longest shortfall?
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ldr longest, [state, #LONGEST_SHORTFALL] // longest = state.longest_shortfall // 2
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cmp length, longest // if length <= longest: // 1
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blt loop // goto loop // 1 thru, 3 taken
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str length, [state, #LONGEST_SHORTFALL] // state.longest_shortfall = length // 2
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// Is this shortfall long enough to trigger a timeout?
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ldr limit, [state, #SHORTFALL_LIMIT] // limit = state.shortfall_limit // 2
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cmp limit, #0 // if limit == 0: // 1
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beq loop // goto loop // 1 thru, 3 taken
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cmp length, limit // if length < limit: // 1
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blt loop // goto loop // 1 thru, 3 taken
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// If so, reset mode to idle and return to idle loop.
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mode .req r3
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mov mode, #MODE_IDLE // mode = MODE_IDLE // 1
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str mode, [state, #MODE] // state.mode = mode // 2
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b idle // goto idle // 3
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.endm
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// Entry point. At this point, the libopencm3 startup code has set things up as
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// normal; .data and .bss are initialised, the stack is set up, etc. However,
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// we don't actually use any of that. All the code in this file would work
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// fine if the M0 jumped straight to main at reset.
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.global main
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.thumb_func
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main: // Cycle counts:
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// Initialise registers used for constant values.
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value .req r0
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ldr sgpio_int, =SGPIO_EXCHANGE_INTERRUPT_BASE // sgpio_int = SGPIO_INT_BASE // 2
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ldr sgpio_data, =SGPIO_SHADOW_REGISTERS_BASE // sgpio_data = SGPIO_REG_SS // 2
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ldr value, =(TARGET_BUFFER_SIZE - 32) // value = TARGET_BUFFER_SIZE - 32 // 2
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mov buf_size_minus_32, value // buf_size_minus_32 = value // 1
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ldr value, =TARGET_DATA_BUFFER // value = TARGET_DATA_BUFFER // 2
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mov buf_base, value // buf_base = value // 1
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ldr value, =TARGET_BUFFER_MASK // value = TARGET_DATA_MASK // 2
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mov buf_mask, value // buf_mask = value // 1
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ldr value, =STATE_BASE // value = STATE_BASE // 2
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mov state, value // state = value // 1
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zero .req r0
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mov zero, #0 // zero = 0 // 1
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mov hi_zero, zero // hi_zero = zero // 1
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// Initialise state.
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str zero, [state, #MODE] // state.mode = zero // 2
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str zero, [state, #M0_COUNT] // state.m0_count = zero // 2
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str zero, [state, #M4_COUNT] // state.m4_count = zero // 2
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str zero, [state, #NUM_SHORTFALLS] // state.num_shortfalls = zero // 2
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str zero, [state, #LONGEST_SHORTFALL] // state.longest_shortfall = zero // 2
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str zero, [state, #SHORTFALL_LIMIT] // state.shortfall_limit = zero // 2
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idle:
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// Wait for RX or TX mode to be set.
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mode .req r3
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ldr mode, [state, #MODE] // mode = state.mode // 2
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cmp mode, #MODE_IDLE // if mode == IDLE: // 1
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beq idle // goto idle // 1 thru, 3 taken
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// Reset counts.
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reset_counts // reset_counts() // 10
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loop:
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// Wait for and clear SGPIO interrupt.
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await_sgpio // await_sgpio() // 34
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// Update buffer pointer.
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update_buf_ptr // update_buf_ptr() // 5
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// Load mode.
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mode .req r3
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ldr mode, [state, #MODE] // mode = state.mode // 2
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// Branch according to mode setting.
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cmp mode, #MODE_RX // if mode == RX: // 1
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beq direction_rx // goto direction_rx // 1 thru, 3 taken
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blt idle // elif mode < RX: goto idle // 1 thru, 3 taken
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direction_tx:
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// Check if there is enough data in the buffer.
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//
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// The number of bytes in the buffer is given by (m4_count - m0_count).
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// We need 32 bytes available to proceed. So our margin, which we want
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// to be positive or zero, is:
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//
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// buf_margin = m4_count - m0_count - 32
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//
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// If there is insufficient data, transmit zeros instead.
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buf_margin .req r0
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ldr buf_margin, [state, #M4_COUNT] // buf_margin = m4_count // 2
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sub buf_margin, count // buf_margin -= count // 1
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sub buf_margin, #32 // buf_margin -= 32 // 1
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bmi tx_zeros // if buf_margin < 0: goto tx_zeros // 1 thru, 3 taken
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// At this point we know there is TX data available.
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// If still in TX start mode, switch to TX run.
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cmp mode, #MODE_TX_START // if mode != TX_START: // 1
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bne tx_write // goto tx_write // 1 thru, 3 taken
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mov mode, #MODE_TX_RUN // mode = TX_RUN // 1
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str mode, [state, #MODE] // state.mode = mode // 2
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tx_write:
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// Write data to SGPIO.
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ldm buf_ptr!, {r0-r3} // r0-r3 = buf_ptr[0:16]; buf_ptr += 16 // 5
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str r0, [sgpio_data, #SLICE0] // SGPIO_REG_SS[SLICE0] = r0 // 8
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str r1, [sgpio_data, #SLICE1] // SGPIO_REG_SS[SLICE1] = r1 // 8
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str r2, [sgpio_data, #SLICE2] // SGPIO_REG_SS[SLICE2] = r2 // 8
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str r3, [sgpio_data, #SLICE3] // SGPIO_REG_SS[SLICE3] = r3 // 8
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ldm buf_ptr!, {r0-r3} // r0-r3 = buf_ptr[0:16]; buf_ptr += 16 // 5
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str r0, [sgpio_data, #SLICE4] // SGPIO_REG_SS[SLICE4] = r0 // 8
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str r1, [sgpio_data, #SLICE5] // SGPIO_REG_SS[SLICE5] = r1 // 8
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str r2, [sgpio_data, #SLICE6] // SGPIO_REG_SS[SLICE6] = r2 // 8
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str r3, [sgpio_data, #SLICE7] // SGPIO_REG_SS[SLICE7] = r3 // 8
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b done // goto done // 3
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tx_zeros:
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// Write zeros to SGPIO.
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mov zero, #0 // zero = 0 // 1
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str zero, [sgpio_data, #SLICE0] // SGPIO_REG_SS[SLICE0] = zero // 8
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str zero, [sgpio_data, #SLICE1] // SGPIO_REG_SS[SLICE1] = zero // 8
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str zero, [sgpio_data, #SLICE2] // SGPIO_REG_SS[SLICE2] = zero // 8
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str zero, [sgpio_data, #SLICE3] // SGPIO_REG_SS[SLICE3] = zero // 8
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str zero, [sgpio_data, #SLICE4] // SGPIO_REG_SS[SLICE4] = zero // 8
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str zero, [sgpio_data, #SLICE5] // SGPIO_REG_SS[SLICE5] = zero // 8
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str zero, [sgpio_data, #SLICE6] // SGPIO_REG_SS[SLICE6] = zero // 8
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str zero, [sgpio_data, #SLICE7] // SGPIO_REG_SS[SLICE7] = zero // 8
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// If in TX start mode, don't count this as a shortfall.
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cmp mode, #MODE_TX_START // if mode == TX_START: // 1
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beq loop // goto loop // 1 thru, 3 taken
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shortfall:
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handle_shortfall // handle_shortfall() // 24
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direction_rx:
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// Check if there is enough space in the buffer.
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//
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// The number of bytes in the buffer is given by (m0_count - m4_count).
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// We need space for another 32 bytes to proceed. So our margin, which
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// we want to be positive or zero, is:
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//
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// buf_margin = buf_size - (m0_count - state.m4_count) - 32
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//
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// which can be rearranged for efficiency as:
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//
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// buf_margin = m4_count + (buf_size - 32) - m0_count
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//
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// If there is insufficient space, jump to shortfall handling.
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buf_margin .req r0
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ldr buf_margin, [state, #M4_COUNT] // buf_margin = state.m4_count // 2
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add buf_margin, buf_size_minus_32 // buf_margin += buf_size_minus_32 // 1
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sub buf_margin, count // buf_margin -= count // 1
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bmi shortfall // if buf_margin < 0: goto shortfall // 1 thru, 3 taken
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// Read data from SGPIO.
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ldr r0, [sgpio_data, #SLICE0] // r0 = SGPIO_REG_SS[SLICE0] // 10
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ldr r1, [sgpio_data, #SLICE1] // r1 = SGPIO_REG_SS[SLICE1] // 10
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ldr r2, [sgpio_data, #SLICE2] // r2 = SGPIO_REG_SS[SLICE2] // 10
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ldr r3, [sgpio_data, #SLICE3] // r3 = SGPIO_REG_SS[SLICE3] // 10
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stm buf_ptr!, {r0-r3} // buf_ptr[0:16] = r0-r3; buf_ptr += 16 // 5
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ldr r0, [sgpio_data, #SLICE4] // r0 = SGPIO_REG_SS[SLICE4] // 10
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ldr r1, [sgpio_data, #SLICE5] // r1 = SGPIO_REG_SS[SLICE5] // 10
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ldr r2, [sgpio_data, #SLICE6] // r2 = SGPIO_REG_SS[SLICE6] // 10
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ldr r3, [sgpio_data, #SLICE7] // r3 = SGPIO_REG_SS[SLICE7] // 10
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stm buf_ptr!, {r0-r3} // buf_ptr[0:16] = r0-r3; buf_ptr += 16 // 5
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done:
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update_counts // update_counts() // 4
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b loop // goto loop // 3
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// The linker will put a literal pool here, so add a label for clearer objdump output:
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constants:
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