dc67fbd2ee
TIMER3 match register 3 was interfering with SCT, fixed by turning off all ORing of timer outputs with SCT outputs.
116 lines
3.8 KiB
C
116 lines
3.8 KiB
C
/*
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* Copyright 2022 Great Scott Gadgets
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*
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* This file is part of HackRF.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 51 Franklin Street,
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* Boston, MA 02110-1301, USA.
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*/
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#include "gpdma.h"
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#include <libopencm3/lpc43xx/timer.h>
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#include <libopencm3/lpc43xx/scu.h>
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#include <libopencm3/lpc43xx/gima.h>
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#include <libopencm3/lpc43xx/creg.h>
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#include <stdint.h>
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#define CLOCK_CYCLES_1_MS (204000)
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#define MEASUREMENT_WINDOW_MS (50)
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#define MEASUREMENT_CYCLES (CLOCK_CYCLES_1_MS * MEASUREMENT_WINDOW_MS)
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/* DMA linked list item */
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typedef struct {
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uint32_t src;
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uint32_t dest;
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uint32_t next_lli;
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uint32_t control;
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} dma_lli;
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/* timer control register configuration sequence */
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typedef struct {
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uint32_t first_tcr;
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uint32_t second_tcr;
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} tcr_sequence;
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dma_lli timer_dma_lli;
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tcr_sequence reset;
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void clkin_detect_init(void)
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{
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/* Timer3 triggers periodic measurement */
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timer_set_prescaler(TIMER3, 0);
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timer_set_mode(TIMER3, TIMER_CTCR_MODE_TIMER);
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TIMER3_MCR = TIMER_MCR_MR0R;
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TIMER3_EMR = (TIMER_EMR_EMC_SET << TIMER_EMR_EMC0_SHIFT) |
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(TIMER_EMR_EMC_TOGGLE << TIMER_EMR_EMC3_SHIFT);
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TIMER3_MR3 = MEASUREMENT_CYCLES;
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TIMER3_MR0 = MEASUREMENT_CYCLES;
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CREG_CREG6 |= CREG_CREG6_CTOUTCTRL;
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/* Timer0 counts CLKIN */
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timer_set_prescaler(TIMER0, 0);
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TIMER0_CCR = TIMER_CCR_CAP3RE;
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GIMA_CAP0_3_IN = 0x20; // T3_MAT3
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/* measure CLKIN signal on P2_5, pin 91, CTIN_2 */
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TIMER0_CTCR = TIMER_CTCR_MODE_COUNTER_RISING | TIMER_CTCR_CINSEL_CAPN_2;
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scu_pinmux(P2_5, SCU_GPIO_PDN | SCU_CONF_FUNCTION1);
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GIMA_CAP0_2_IN = 0x00; // CTIN_2
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// temporarily testing with T0_CAP1, P1_12, pin 56, P28 pin 4
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//TIMER0_CTCR = TIMER_CTCR_MODE_COUNTER_RISING | TIMER_CTCR_CINSEL_CAPN_1;
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//scu_pinmux(P1_12, SCU_GPIO_PDN | SCU_CONF_FUNCTION4);
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//GIMA_CAP0_1_IN = 0x20; // T0_CAP1
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reset.first_tcr = TIMER_TCR_CEN | TIMER_TCR_CRST;
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reset.second_tcr = TIMER_TCR_CEN;
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timer_dma_lli.src = (uint32_t) & (reset);
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timer_dma_lli.dest = (uint32_t) & (TIMER0_TCR);
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timer_dma_lli.next_lli = (uint32_t) & (timer_dma_lli);
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timer_dma_lli.control = GPDMA_CCONTROL_TRANSFERSIZE(2) |
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GPDMA_CCONTROL_SBSIZE(0) // 1
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| GPDMA_CCONTROL_DBSIZE(0) // 1
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| GPDMA_CCONTROL_SWIDTH(2) // 32-bit word
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| GPDMA_CCONTROL_DWIDTH(2) // 32-bit word
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| GPDMA_CCONTROL_S(0) // AHB Master 0
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| GPDMA_CCONTROL_D(1) // AHB Master 1
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| GPDMA_CCONTROL_SI(1) // increment source
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| GPDMA_CCONTROL_DI(0) // do not increment destination
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| GPDMA_CCONTROL_PROT1(0) // user mode
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| GPDMA_CCONTROL_PROT2(0) // not bufferable
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| GPDMA_CCONTROL_PROT3(0) // not cacheable
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| GPDMA_CCONTROL_I(0); // interrupt disabled
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gpdma_controller_enable();
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GPDMA_C0SRCADDR = timer_dma_lli.src;
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GPDMA_C0DESTADDR = timer_dma_lli.dest;
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GPDMA_C0LLI = timer_dma_lli.next_lli;
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GPDMA_C0CONTROL = timer_dma_lli.control;
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GPDMA_C0CONFIG = GPDMA_CCONFIG_DESTPERIPHERAL(0x7) // T3_MAT0
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| GPDMA_CCONFIG_FLOWCNTRL(1) // memory-to-peripheral
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| GPDMA_CCONFIG_H(0); // do not halt
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gpdma_channel_enable(0);
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/* start counting */
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timer_reset(TIMER0);
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timer_reset(TIMER3);
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timer_enable_counter(TIMER0);
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timer_enable_counter(TIMER3);
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}
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uint32_t clkin_frequency(void)
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{
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return TIMER0_CR3 * (1000 / MEASUREMENT_WINDOW_MS);
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};
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