315 lines
8.4 KiB
C
315 lines
8.4 KiB
C
/*
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* Copyright 2012 Michael Ossmann <mike@ossmann.com>
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* Copyright 2012 Jared Boone <jared@sharebrained.com>
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*
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* This file is part of HackRF.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 51 Franklin Street,
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* Boston, MA 02110-1301, USA.
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*/
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#include "si5351c.h"
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#include <libopencm3/lpc43xx/i2c.h>
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enum pll_sources active_clock_source;
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/* FIXME return i2c0 status from each function */
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/* write to single register */
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void si5351c_write_single(uint8_t reg, uint8_t val)
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{
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i2c0_tx_start();
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i2c0_tx_byte(SI5351C_I2C_ADDR | I2C_WRITE);
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i2c0_tx_byte(reg);
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i2c0_tx_byte(val);
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i2c0_stop();
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}
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/* read single register */
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uint8_t si5351c_read_single(uint8_t reg)
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{
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uint8_t val;
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/* set register address with write */
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i2c0_tx_start();
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i2c0_tx_byte(SI5351C_I2C_ADDR | I2C_WRITE);
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i2c0_tx_byte(reg);
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/* read the value */
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i2c0_tx_start();
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i2c0_tx_byte(SI5351C_I2C_ADDR | I2C_READ);
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val = i2c0_rx_byte();
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i2c0_stop();
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return val;
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}
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/*
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* Write to one or more contiguous registers. data[0] should be the first
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* register number, one or more values follow.
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*/
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void si5351c_write(uint8_t* const data, const uint_fast8_t data_count)
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{
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uint_fast8_t i;
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i2c0_tx_start();
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i2c0_tx_byte(SI5351C_I2C_ADDR | I2C_WRITE);
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for (i = 0; i < data_count; i++)
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i2c0_tx_byte(data[i]);
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i2c0_stop();
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}
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/* Disable all CLKx outputs. */
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void si5351c_disable_all_outputs()
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{
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uint8_t data[] = { 3, 0xFF };
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si5351c_write(data, sizeof(data));
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}
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/* Turn off OEB pin control for all CLKx */
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void si5351c_disable_oeb_pin_control()
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{
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uint8_t data[] = { 9, 0xFF };
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si5351c_write(data, sizeof(data));
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}
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/* Power down all CLKx */
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void si5351c_power_down_all_clocks()
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{
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uint8_t data[] = { 16
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, SI5351C_CLK_POWERDOWN
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, SI5351C_CLK_POWERDOWN
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, SI5351C_CLK_POWERDOWN
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, SI5351C_CLK_POWERDOWN
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, SI5351C_CLK_POWERDOWN
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, SI5351C_CLK_POWERDOWN
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, SI5351C_CLK_POWERDOWN | SI5351C_CLK_INT_MODE
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, SI5351C_CLK_POWERDOWN | SI5351C_CLK_INT_MODE
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};
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si5351c_write(data, sizeof(data));
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}
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/*
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* Register 183: Crystal Internal Load Capacitance
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* Reads as 0xE4 on power-up
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* Set to 8pF based on crystal specs and HackRF One testing
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*/
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void si5351c_set_crystal_configuration()
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{
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uint8_t data[] = { 183, 0x80 };
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si5351c_write(data, sizeof(data));
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}
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/*
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* Register 187: Fanout Enable
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* Turn on XO and MultiSynth fanout only.
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*/
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void si5351c_enable_xo_and_ms_fanout()
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{
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uint8_t data[] = { 187, 0xD0 };
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si5351c_write(data, sizeof(data));
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}
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/*
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* Register 15: PLL Input Source
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* CLKIN_DIV=0 (Divide by 1)
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* PLLA_SRC=0 (XTAL)
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* PLLB_SRC=1 (CLKIN)
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*/
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void si5351c_configure_pll_sources(void)
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{
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uint8_t data[] = { 15, 0x08 };
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si5351c_write(data, sizeof(data));
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}
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/* MultiSynth NA (PLLA) and NB (PLLB) */
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void si5351c_configure_pll_multisynth(void)
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{
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//init plla to (0x0e00+512)/128*25mhz xtal = 800mhz -> int mode
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uint8_t data[] = { 26, 0x00, 0x01, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x00 };
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si5351c_write(data, sizeof(data));
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/* 10 MHz input on CLKIN for PLLB */
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data[0] = 34;
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data[4] = 0x26;
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si5351c_write(data, sizeof(data));
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}
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void si5351c_reset_pll(void)
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{
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/* reset PLLA and PLLB */
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uint8_t data[] = { 177, 0xA0 };
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si5351c_write(data, sizeof(data));
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}
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void si5351c_configure_multisynth(const uint_fast8_t ms_number,
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const uint32_t p1, const uint32_t p2, const uint32_t p3,
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const uint_fast8_t r_div)
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{
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/*
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* TODO: Check for p3 > 0? 0 has no meaning in fractional mode?
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* And it makes for more jitter in integer mode.
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*/
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/*
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* r is the r divider value encoded:
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* 0 means divide by 1
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* 1 means divide by 2
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* 2 means divide by 4
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* ...
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* 7 means divide by 128
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*/
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const uint_fast8_t register_number = 42 + (ms_number * 8);
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uint8_t data[] = {
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register_number,
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(p3 >> 8) & 0xFF,
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(p3 >> 0) & 0xFF,
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(r_div << 4) | (0 << 2) | ((p1 >> 16) & 0x3),
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(p1 >> 8) & 0xFF,
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(p1 >> 0) & 0xFF,
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(((p3 >> 16) & 0xF) << 4) | (((p2 >> 16) & 0xF) << 0),
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(p2 >> 8) & 0xFF,
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(p2 >> 0) & 0xFF };
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si5351c_write(data, sizeof(data));
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}
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#ifdef JELLYBEAN
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/*
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* Registers 16 through 23: CLKx Control
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* CLK0:
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* CLK0_PDN=0 (powered up)
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* MS0_INT=1 (integer mode)
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* MS0_SRC=0 (PLLA as source for MultiSynth 0)
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* CLK0_INV=0 (not inverted)
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* CLK0_SRC=3 (MS0 as input source)
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* CLK0_IDRV=3 (8mA)
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* CLK1:
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* CLK1_PDN=0 (powered up)
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* MS1_INT=1 (integer mode)
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* MS1_SRC=0 (PLLA as source for MultiSynth 1)
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* CLK1_INV=0 (not inverted)
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* CLK1_SRC=2 (MS0 as input source)
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* CLK1_IDRV=3 (8mA)
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* CLK2:
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* CLK2_PDN=0 (powered up)
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* MS2_INT=1 (integer mode)
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* MS2_SRC=0 (PLLA as source for MultiSynth 2)
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* CLK2_INV=0 (not inverted)
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* CLK2_SRC=2 (MS0 as input source)
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* CLK2_IDRV=3 (8mA)
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* CLK3:
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* CLK3_PDN=0 (powered up)
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* MS3_INT=1 (integer mode)
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* MS3_SRC=0 (PLLA as source for MultiSynth 3)
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* CLK3_INV=0 (inverted)
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* CLK3_SRC=2 (MS0 as input source)
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* CLK3_IDRV=3 (8mA)
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* CLK4:
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* CLK4_PDN=0 (powered up)
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* MS4_INT=0 (fractional mode -- to support 12MHz to LPC for USB DFU)
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* MS4_SRC=0 (PLLA as source for MultiSynth 4)
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* CLK4_INV=0 (not inverted)
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* CLK4_SRC=3 (MS4 as input source)
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* CLK4_IDRV=3 (8mA)
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* CLK5:
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* CLK5_PDN=0 (powered up)
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* MS5_INT=1 (integer mode)
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* MS5_SRC=0 (PLLA as source for MultiSynth 5)
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* CLK5_INV=0 (not inverted)
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* CLK5_SRC=3 (MS5 as input source)
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* CLK5_IDRV=3 (8mA)
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*/
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void si5351c_configure_clock_control()
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{
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uint8_t data[] = { 16, 0x4F, 0x4B, 0x4B, 0x4B, 0x0F, 0x4F, 0xC0, 0xC0 };
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si5351c_write(data, sizeof(data));
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}
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#endif
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#if (defined JAWBREAKER || defined HACKRF_ONE)
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void si5351c_configure_clock_control(const enum pll_sources source)
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{
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uint8_t pll;
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if (source == PLL_SOURCE_CLKIN) {
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/* PLLB on CLKIN */
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pll = SI5351C_CLK_PLL_SRC_B;
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} else {
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/* PLLA on XTAL */
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pll = SI5351C_CLK_PLL_SRC_A;
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}
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uint8_t data[] = {16
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,SI5351C_CLK_FRAC_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_2MA)
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,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_0_4) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_2MA)
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,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_0_4) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_2MA)
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,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_8MA)
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,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_6MA)
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,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_4MA)
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,SI5351C_CLK_POWERDOWN | SI5351C_CLK_INT_MODE /*not connected, but: plla int mode*/
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,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_8MA)
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};
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si5351c_write(data, sizeof(data));
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}
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#endif
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/* Enable CLK outputs 0, 1, 2, 3, 4, 5, 7 only. */
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void si5351c_enable_clock_outputs()
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{
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uint8_t data[] = { 3, 0x40 };
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si5351c_write(data, sizeof(data));
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}
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void si5351c_set_int_mode(const uint_fast8_t ms_number, const uint_fast8_t on){
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uint8_t data[] = {16, 0};
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if(ms_number < 8){
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data[0] = 16 + ms_number;
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data[1] = si5351c_read_single(data[0]);
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if(on)
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data[1] |= SI5351C_CLK_INT_MODE;
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else
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data[1] &= ~(SI5351C_CLK_INT_MODE);
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si5351c_write(data, 2);
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}
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}
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void si5351c_set_clock_source(const enum pll_sources source)
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{
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si5351c_configure_clock_control(source);
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active_clock_source = source;
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}
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void si5351c_activate_best_clock_source(void)
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{
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uint8_t device_status = si5351c_read_single(0);
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if (device_status & SI5351C_LOS) {
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/* CLKIN not detected */
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if (active_clock_source == PLL_SOURCE_CLKIN) {
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si5351c_set_clock_source(PLL_SOURCE_XTAL);
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}
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} else {
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/* CLKIN detected */
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if (active_clock_source == PLL_SOURCE_XTAL) {
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si5351c_set_clock_source(PLL_SOURCE_CLKIN);
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}
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}
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}
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