Jared Boone 9a53fd3a07 New CPLD .svf. ...

Change Si5351C CLK2 to 10MHz.
Keep CLK3 at 20MHz, but not inverted.
Source SGPIO8 from P1_12 instead of P9_6. (See "SGPIO Clock Routing") modification at https://github.com/mossmann/hackrf/wiki/Future-Hardware-Modifications ).

2012-06-15 16:12:35 -07:00

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jellybean

New CPLD .svf.

2012-06-15 16:12:35 -07:00

kicad

updated SMA module to match CONREVSMA003.062 recommended footprint

2012-06-03 20:13:02 -06:00

lemondrop

fixed balun pin order

2012-05-06 16:09:00 -06:00

lollipop

completed BOM info

2012-06-04 14:44:25 -06:00

test

noting discrepancy between implementations

2012-06-13 21:27:14 -06:00