839a1a170f
pins b7 & b6 are floating, disable re-triggering selecting a different HPC_STOP fixes the dc offset drift disabling and enabling rx/tx after tuning triggers the dc offset correction
438 lines
9.9 KiB
C
438 lines
9.9 KiB
C
/*
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* 'gcc -DTEST -DDEBUG -O2 -o test max2837.c' prints out what test
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* program would do if it had a real spi library
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*
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* 'gcc -DTEST -DBUS_PIRATE -O2 -o test max2837.c' prints out bus
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* pirate commands to do the same thing.
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*/
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#include <stdint.h>
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#include <string.h>
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#include "max2837.h"
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#include "max2837_regs.def" // private register def macros
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#if (defined DEBUG || defined BUS_PIRATE)
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#include <stdio.h>
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#define LOG printf
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#else
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#define LOG(x,...)
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#include <libopencm3/lpc43xx/ssp.h>
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#include <libopencm3/lpc43xx/scu.h>
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#include <libopencm3/lpc43xx/gpio.h>
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#include "hackrf_core.h"
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#endif
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/* Default register values. */
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static uint16_t max2837_regs_default[MAX2837_NUM_REGS] = {
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0x150, /* 0 */
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0x002, /* 1 */
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0x1f4, /* 2 */
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0x1b9, /* 3 */
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0x00a, /* 4 */
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0x080, /* 5 */
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0x006, /* 6 */
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0x000, /* 7 */
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0x080, /* 8 */
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0x018, /* 9 */
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0x058, /* 10 */
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0x016, /* 11 */
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0x24f, /* 12 */
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0x150, /* 13 */
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0x1c5, /* 14 */
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0x081, /* 15 */
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0x01c, /* 16 */
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0x155, /* 17 */
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0x155, /* 18 */
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0x153, /* 19 */
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0x241, /* 20 */
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/*
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* Charge Pump Common Mode Enable bit (0) of register 21 must be set or TX
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* does not work. Page 1 of the SPI doc says not to set it (0x02c), but
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* page 21 says it should be set by default (0x02d).
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*/
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0x02d, /* 21 */
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0x1a9, /* 22 */
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0x24f, /* 23 */
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0x180, /* 24 */
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0x100, /* 25 */
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0x3ca, /* 26 */
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0x3e3, /* 27 */
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0x0c0, /* 28 */
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0x3f0, /* 29 */
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0x080, /* 30 */
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0x000 }; /* 31 */
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uint16_t max2837_regs[MAX2837_NUM_REGS];
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/* Mark all regsisters dirty so all will be written at init. */
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uint32_t max2837_regs_dirty = 0xffffffff;
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/* Set up all registers according to defaults specified in docs. */
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void max2837_init(void)
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{
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LOG("# max2837_init\n");
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memcpy(max2837_regs, max2837_regs_default, sizeof(max2837_regs));
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max2837_regs_dirty = 0xffffffff;
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/* Write default register values to chip. */
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max2837_regs_commit();
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}
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/*
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* Set up pins for GPIO and SPI control, configure SSP peripheral for SPI, and
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* set our own default register configuration.
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*/
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void max2837_setup(void)
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{
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LOG("# max2837_setup\n");
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#if !defined TEST
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/* Configure XCVR_CTL GPIO pins. */
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#ifdef JELLYBEAN
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scu_pinmux(SCU_XCVR_RXHP, SCU_GPIO_FAST);
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scu_pinmux(SCU_XCVR_B1, SCU_GPIO_FAST);
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scu_pinmux(SCU_XCVR_B2, SCU_GPIO_FAST);
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scu_pinmux(SCU_XCVR_B3, SCU_GPIO_FAST);
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scu_pinmux(SCU_XCVR_B4, SCU_GPIO_FAST);
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scu_pinmux(SCU_XCVR_B5, SCU_GPIO_FAST);
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scu_pinmux(SCU_XCVR_B6, SCU_GPIO_FAST);
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scu_pinmux(SCU_XCVR_B7, SCU_GPIO_FAST);
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#endif
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scu_pinmux(SCU_XCVR_ENABLE, SCU_GPIO_FAST);
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scu_pinmux(SCU_XCVR_RXENABLE, SCU_GPIO_FAST);
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scu_pinmux(SCU_XCVR_TXENABLE, SCU_GPIO_FAST);
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/* Set GPIO pins as outputs. */
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GPIO2_DIR |= (PIN_XCVR_ENABLE | PIN_XCVR_RXENABLE | PIN_XCVR_TXENABLE);
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#ifdef JELLYBEAN
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GPIO_DIR(PORT_XCVR_RXHP) |= PIN_XCVR_RXHP;
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GPIO_DIR(PORT_XCVR_B) |=
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PIN_XCVR_B1
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| PIN_XCVR_B2
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| PIN_XCVR_B3
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| PIN_XCVR_B4
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| PIN_XCVR_B5
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| PIN_XCVR_B6
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| PIN_XCVR_B7
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;
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#endif
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/* disable everything */
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gpio_clear(PORT_XCVR_ENABLE,
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(PIN_XCVR_ENABLE | PIN_XCVR_RXENABLE | PIN_XCVR_TXENABLE));
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#ifdef JELLYBEAN
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gpio_set(PORT_XCVR_RXHP, PIN_XCVR_RXHP);
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gpio_set(PORT_XCVR_B,
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PIN_XCVR_B1
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| PIN_XCVR_B2
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| PIN_XCVR_B3
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| PIN_XCVR_B4
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| PIN_XCVR_B5
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| PIN_XCVR_B6
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| PIN_XCVR_B7
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);
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#endif
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#endif
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max2837_init();
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LOG("# max2837_init done\n");
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/* Use SPI control instead of B1-B7 pins for gain settings. */
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set_MAX2837_TXVGA_GAIN_SPI_EN(1);
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set_MAX2837_TXVGA_GAIN_MSB_SPI_EN(1);
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//set_MAX2837_TXVGA_GAIN(0x3f); /* maximum attenuation */
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set_MAX2837_TXVGA_GAIN(0x00); /* minimum attenuation */
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set_MAX2837_VGAMUX_enable(1);
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set_MAX2837_VGA_EN(1);
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set_MAX2837_HPC_RXGAIN_EN(0);
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set_MAX2837_HPC_STOP(MAX2837_STOP_1K);
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set_MAX2837_LNAgain_SPI_EN(1);
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set_MAX2837_LNAgain(MAX2837_LNAgain_MAX); /* maximum gain */
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set_MAX2837_VGAgain_SPI_EN(1);
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set_MAX2837_VGA(0x18); /* reasonable gain for noisy 2.4GHz environment */
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/* maximum rx output common-mode voltage */
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set_MAX2837_BUFF_VCM(MAX2837_BUFF_VCM_1_25);
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/* configure baseband filter for 8 MHz TX */
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set_MAX2837_LPF_EN(1);
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set_MAX2837_ModeCtrl(MAX2837_ModeCtrl_RxLPF);
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set_MAX2837_FT(MAX2837_FT_5M);
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max2837_regs_commit();
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}
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/* SPI register read. */
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uint16_t max2837_spi_read(uint8_t r) {
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gpio_clear(PORT_XCVR_CS, PIN_XCVR_CS);
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const uint16_t value = ssp_transfer(SSP1_NUM, (uint16_t)((1 << 15) | (r << 10)));
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gpio_set(PORT_XCVR_CS, PIN_XCVR_CS);
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return value & 0x3ff;
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}
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/* SPI register write */
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void max2837_spi_write(uint8_t r, uint16_t v) {
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#ifdef BUS_PIRATE
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LOG("{0x%02x 0x%02x]\n", 0x00 | ((uint16_t)r<<2) | ((v>>8) & 0x3),
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v & 0xff);
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#elif DEBUG
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LOG("0x%03x -> reg%d\n", v, r);
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#else
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gpio_clear(PORT_XCVR_CS, PIN_XCVR_CS);
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ssp_transfer(SSP1_NUM, (uint16_t)((r << 10) | (v & 0x3ff)));
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gpio_set(PORT_XCVR_CS, PIN_XCVR_CS);
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#endif
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}
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uint16_t max2837_reg_read(uint8_t r)
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{
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if ((max2837_regs_dirty >> r) & 0x1) {
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max2837_spi_read(r);
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};
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return max2837_regs[r];
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}
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void max2837_reg_write(uint8_t r, uint16_t v)
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{
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max2837_regs[r] = v;
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max2837_spi_write(r, v);
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MAX2837_REG_SET_CLEAN(r);
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}
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/* This functions should not be needed, and might be confusing. DELETE. */
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void max2837_regs_read(void)
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{
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;
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}
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static inline void max2837_reg_commit(uint8_t r)
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{
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max2837_reg_write(r,max2837_regs[r]);
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}
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void max2837_regs_commit(void)
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{
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int r;
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for(r = 0; r < MAX2837_NUM_REGS; r++) {
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if ((max2837_regs_dirty >> r) & 0x1) {
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max2837_reg_commit(r);
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}
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}
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}
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void max2837_start(void)
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{
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LOG("# max2837_start\n");
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set_MAX2837_EN_SPI(1);
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max2837_regs_commit();
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#if !defined TEST
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gpio_clear(PORT_XCVR_ENABLE, (PIN_XCVR_RXENABLE | PIN_XCVR_TXENABLE));
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gpio_set(PORT_XCVR_ENABLE, PIN_XCVR_ENABLE);
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#endif
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}
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void max2837_tx(void)
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{
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LOG("# max2837_tx\n");
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#if !defined TEST
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set_MAX2837_ModeCtrl(MAX2837_ModeCtrl_TxLPF);
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max2837_regs_commit();
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gpio_clear(PORT_XCVR_ENABLE, PIN_XCVR_RXENABLE);
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gpio_set(PORT_XCVR_ENABLE, PIN_XCVR_TXENABLE);
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#endif
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}
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void max2837_rx(void)
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{
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LOG("# max2837_rx\n");
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set_MAX2837_ModeCtrl(MAX2837_ModeCtrl_RxLPF);
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max2837_regs_commit();
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#if !defined TEST
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gpio_clear(PORT_XCVR_ENABLE, PIN_XCVR_TXENABLE);
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gpio_set(PORT_XCVR_ENABLE, PIN_XCVR_RXENABLE);
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#endif
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}
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void max2837_stop(void)
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{
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LOG("# max2837_stop\n");
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set_MAX2837_EN_SPI(0);
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max2837_regs_commit();
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#if !defined TEST
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gpio_clear(PORT_XCVR_ENABLE,
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(PIN_XCVR_ENABLE | PIN_XCVR_RXENABLE | PIN_XCVR_TXENABLE));
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#endif
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}
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void max2837_set_frequency(uint32_t freq)
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{
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uint8_t band;
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uint8_t lna_band;
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uint32_t div_frac;
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uint32_t div_int;
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uint32_t div_rem;
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uint32_t div_cmp;
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int i;
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/* Select band. Allow tuning outside specified bands. */
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if (freq < 2400000000U) {
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band = MAX2837_LOGEN_BSW_2_3;
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lna_band = MAX2837_LNAband_2_4;
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}
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else if (freq < 2500000000U) {
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band = MAX2837_LOGEN_BSW_2_4;
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lna_band = MAX2837_LNAband_2_4;
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}
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else if (freq < 2600000000U) {
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band = MAX2837_LOGEN_BSW_2_5;
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lna_band = MAX2837_LNAband_2_6;
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}
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else {
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band = MAX2837_LOGEN_BSW_2_6;
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lna_band = MAX2837_LNAband_2_6;
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}
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LOG("# max2837_set_frequency %ld, band %d, lna band %d\n",
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freq, band, lna_band);
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/* ASSUME 40MHz PLL. Ratio = F*(4/3)/40,000,000 = F/30,000,000 */
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div_int = freq / 30000000;
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div_rem = freq % 30000000;
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div_frac = 0;
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div_cmp = 30000000;
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for( i = 0; i < 20; i++) {
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div_frac <<= 1;
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div_cmp >>= 1;
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if (div_rem > div_cmp) {
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div_frac |= 0x1;
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div_rem -= div_cmp;
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}
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}
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LOG("# int %ld, frac %ld\n", div_int, div_frac);
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/* Band settings */
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set_MAX2837_LOGEN_BSW(band);
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set_MAX2837_LNAband(lna_band);
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/* Write order matters here, so commit INT and FRAC_HI before
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* committing FRAC_LO, which is the trigger for VCO
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* auto-select. TODO - it's cleaner this way, but it would be
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* faster to explicitly commit the registers explicitly so the
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* dirty bits aren't scanned twice. */
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set_MAX2837_SYN_INT(div_int);
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set_MAX2837_SYN_FRAC_HI((div_frac >> 10) & 0x3ff);
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max2837_regs_commit();
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set_MAX2837_SYN_FRAC_LO(div_frac & 0x3ff);
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max2837_regs_commit();
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}
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typedef struct {
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uint32_t bandwidth_hz;
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uint32_t ft;
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} max2837_ft_t;
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static const max2837_ft_t max2837_ft[] = {
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{ 1750000, MAX2837_FT_1_75M },
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{ 2500000, MAX2837_FT_2_5M },
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{ 3500000, MAX2837_FT_3_5M },
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{ 5000000, MAX2837_FT_5M },
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{ 5500000, MAX2837_FT_5_5M },
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{ 6000000, MAX2837_FT_6M },
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{ 7000000, MAX2837_FT_7M },
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{ 8000000, MAX2837_FT_8M },
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{ 9000000, MAX2837_FT_9M },
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{ 10000000, MAX2837_FT_10M },
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{ 12000000, MAX2837_FT_12M },
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{ 14000000, MAX2837_FT_14M },
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{ 15000000, MAX2837_FT_15M },
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{ 20000000, MAX2837_FT_20M },
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{ 24000000, MAX2837_FT_24M },
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{ 28000000, MAX2837_FT_28M },
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{ 0, 0 },
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};
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bool max2837_set_lpf_bandwidth(const uint32_t bandwidth_hz) {
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const max2837_ft_t* p = max2837_ft;
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while( p->bandwidth_hz != 0 ) {
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if( p->bandwidth_hz >= bandwidth_hz ) {
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break;
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}
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p++;
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}
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if( p->bandwidth_hz != 0 ) {
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set_MAX2837_FT(p->ft);
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max2837_regs_commit();
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return true;
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} else {
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return false;
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}
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}
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bool max2837_set_lna_gain(const uint32_t gain_db) {
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uint16_t val;
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switch(gain_db){
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case 40:
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val = MAX2837_LNAgain_MAX;
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break;
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case 32:
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val = MAX2837_LNAgain_M8;
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break;
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case 24:
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val = MAX2837_LNAgain_M16;
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break;
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case 16:
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val = MAX2837_LNAgain_M24;
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break;
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case 8:
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val = MAX2837_LNAgain_M32;
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break;
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case 0:
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val = MAX2837_LNAgain_M40;
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break;
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default:
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return false;
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}
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set_MAX2837_LNAgain(val);
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max2837_reg_commit(1);
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return true;
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}
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bool max2837_set_vga_gain(const uint32_t gain_db) {
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if( (gain_db & 0x1) || gain_db > 62)/* 0b11111*2 */
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return false;
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set_MAX2837_VGA( 31-(gain_db >> 1) );
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max2837_reg_commit(5);
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return true;
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}
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bool max2837_set_txvga_gain(const uint32_t gain_db) {
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uint16_t val=0;
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if(gain_db <16){
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val = 31-gain_db;
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val |= (1 << 5); // bit6: 16db
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} else{
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val = 31-(gain_db-16);
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}
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set_MAX2837_TXVGA_GAIN(val);
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max2837_reg_commit(29);
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return true;
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}
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#ifdef TEST
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int main(int ac, char **av)
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{
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max2837_setup();
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max2837_set_frequency(2441000000);
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max2837_start();
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max2837_tx();
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max2837_stop();
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}
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#endif //TEST
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