61 lines
1.9 KiB
VHDL
Executable File
61 lines
1.9 KiB
VHDL
Executable File
--
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-- Copyright 2012 Jared Boone
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--
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-- This file is part of HackRF.
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2, or (at your option)
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-- any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; see the file COPYING. If not, write to
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-- the Free Software Foundation, Inc., 51 Franklin Street,
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-- Boston, MA 02110-1301, USA.
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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library UNISIM;
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use UNISIM.vcomponents.all;
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entity top is
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Port(
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SGPIO : inout std_logic_vector(15 downto 0);
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DA : in std_logic_vector(7 downto 0);
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DD : out std_logic_vector(9 downto 0);
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CODEC_CLK : in std_logic;
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CODEC_X2_CLK : in std_logic;
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B1AUX : in std_logic_vector(16 downto 9);
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B2AUX : inout std_logic_vector(16 downto 1)
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);
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end top;
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architecture Behavioral of top is
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type transfer_direction is (to_sgpio, from_sgpio);
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signal transfer_direction_i : transfer_direction;
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begin
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transfer_direction_i <= to_sgpio when B1AUX(9) = '0'
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else from_sgpio;
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DD <= (DD'high => '1', others => '0');
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B2AUX <= SGPIO when transfer_direction_i = from_sgpio
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else (others => 'Z');
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SGPIO <= B2AUX when transfer_direction_i = to_sgpio
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else (others => 'Z');
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end Behavioral;
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