d103c31187
Capture ADC and codec clock state with sufficient timing margin. Increase drive strength on codec clock and invert CPLD capture clock to provide margin for capturing codec clock (I vs. Q channel).
305 lines
12 KiB
C
305 lines
12 KiB
C
/*
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* Copyright 2012 Jared Boone <jared@sharebrained.com>
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* Copyright 2013 Benjamin Vernoux <titanmkd@gmail.com>
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*
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* This file is part of HackRF.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 51 Franklin Street,
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* Boston, MA 02110-1301, USA.
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*/
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#include <libopencm3/lpc43xx/scu.h>
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#include <libopencm3/lpc43xx/sgpio.h>
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#include <hackrf_core.h>
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#include <sgpio.h>
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#ifdef RAD1O
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static void update_q_invert(sgpio_config_t* const config);
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#endif
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void sgpio_configure_pin_functions(sgpio_config_t* const config) {
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scu_pinmux(SCU_PINMUX_SGPIO0, SCU_GPIO_FAST | SCU_CONF_FUNCTION3);
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scu_pinmux(SCU_PINMUX_SGPIO1, SCU_GPIO_FAST | SCU_CONF_FUNCTION3);
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scu_pinmux(SCU_PINMUX_SGPIO2, SCU_GPIO_FAST | SCU_CONF_FUNCTION2);
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scu_pinmux(SCU_PINMUX_SGPIO3, SCU_GPIO_FAST | SCU_CONF_FUNCTION2);
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scu_pinmux(SCU_PINMUX_SGPIO4, SCU_GPIO_FAST | SCU_CONF_FUNCTION2);
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scu_pinmux(SCU_PINMUX_SGPIO5, SCU_GPIO_FAST | SCU_CONF_FUNCTION2);
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scu_pinmux(SCU_PINMUX_SGPIO6, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
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scu_pinmux(SCU_PINMUX_SGPIO7, SCU_GPIO_FAST | SCU_CONF_FUNCTION6);
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scu_pinmux(SCU_PINMUX_SGPIO8, SCU_GPIO_FAST | SCU_CONF_FUNCTION6);
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scu_pinmux(SCU_PINMUX_SGPIO9, SCU_GPIO_FAST | SCU_CONF_FUNCTION7);
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scu_pinmux(SCU_PINMUX_SGPIO10, SCU_GPIO_FAST | SCU_CONF_FUNCTION6);
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scu_pinmux(SCU_PINMUX_SGPIO11, SCU_GPIO_FAST | SCU_CONF_FUNCTION6);
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scu_pinmux(SCU_PINMUX_SGPIO12, SCU_GPIO_FAST | SCU_CONF_FUNCTION0); /* GPIO0[13] */
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scu_pinmux(SCU_PINMUX_SGPIO13, SCU_GPIO_FAST | SCU_CONF_FUNCTION4); /* GPIO5[12] */
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scu_pinmux(SCU_PINMUX_SGPIO14, SCU_GPIO_FAST | SCU_CONF_FUNCTION4); /* GPIO5[13] */
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scu_pinmux(SCU_PINMUX_SGPIO15, SCU_GPIO_FAST | SCU_CONF_FUNCTION4); /* GPIO5[14] */
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sgpio_cpld_stream_rx_set_q_invert(config, 0);
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hw_sync_enable(0);
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gpio_output(config->gpio_rx_q_invert);
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gpio_output(config->gpio_hw_sync_enable);
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}
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void sgpio_set_slice_mode(
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sgpio_config_t* const config,
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const bool multi_slice
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) {
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config->slice_mode_multislice = multi_slice;
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}
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/*
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SGPIO0 to 7 = DAC/ADC data bits 0 to 7 (Nota: DAC is 10bits but only bit9 to bit2 are used bit1 & 0 are forced to 0 by CPLD)
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ADC=> CLK x 2=CLKx2 with CLKx2(0)rising=D0Q, CLKx2(1)rising=D1I (corresponds to CLK(0)falling+tD0Q=>D0Q, CLK(1)rising+tDOI=>D1I, CLK(1)falling+tD0Q=>D1Q, CLK(1)rising+tDOI=>D2I ...)
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tDOI(CLK Rise to I-ADC Channel-I Output Data Valid)=7.4 to 9ns, tD0Q(CLK Fall to Q-ADC Channel-Q Output Data Valid)=6.9 to 9ns
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DAC=> CLK x 2=CLKx2 with CLKx2(0)rising=Q:N-2, CLKx2(1)rising=I:N-1(corresponds to CLK(0)rising=>Q:N-2, CLK(0)falling I:N-1, CLK(1)rising=>Q:N-1, CLK(1)falling I:N ...)
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tDSI(I-DAC Data to CLK Fall Setup Time)=min 10ns, tDSQ(Q-DAC Data to CLK Rise Setup Time)=min 10ns
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SGPIO8 Clock Input (External Clock)
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SGPIO9 Capture Input (Capture/ChipSelect, 1=Enable Capture, 0=Disable capture)
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SGPIO10 Disable Output (1/High=Disable codec data stream, 0/Low=Enable codec data stream)
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SGPIO11 Direction Output (1/High=TX mode LPC43xx=>CPLD=>DAC, 0/Low=RX mode LPC43xx<=CPLD<=ADC)
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*/
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void sgpio_configure(
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sgpio_config_t* const config,
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const sgpio_direction_t direction
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) {
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// Disable all counters during configuration
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SGPIO_CTRL_ENABLE = 0;
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// Set SGPIO output values.
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const uint_fast8_t cpld_direction =
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(direction == SGPIO_DIRECTION_TX) ? 1 : 0;
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SGPIO_GPIO_OUTREG =
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(cpld_direction << 11) /* 1=Output SGPIO11 High(TX mode), 0=Output SGPIO11 Low(RX mode)*/
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| (1L << 10) // disable codec data stream during configuration (Output SGPIO10 High)
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;
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#ifdef RAD1O
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/* The data direction might have changed. Check if we need to
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* adjust the q inversion. */
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update_q_invert(config);
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#endif
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// Enable SGPIO pin outputs.
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const uint_fast16_t sgpio_gpio_data_direction =
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(direction == SGPIO_DIRECTION_TX)
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? (0xFF << 0)
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: (0x00 << 0);
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SGPIO_GPIO_OENREG =
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(1L << 14) // GPDMA burst request SGPIO14 active
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| (1L << 11) // direction output SGPIO11 active
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| (1L << 10) // disable output SGPIO10 active
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| (0L << 9) // capture input SGPIO9 (output i is tri-stated)
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| (0L << 8) // clock input SGPIO8 (output i is tri-stated)
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| sgpio_gpio_data_direction // 0xFF=Output all SGPIO High(TX mode), 0x00=Output all SPGIO Low(RX mode)
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;
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SGPIO_OUT_MUX_CFG( 8) = // SGPIO8: Input: clock
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SGPIO_OUT_MUX_CFG_P_OE_CFG(0) /* 0x0 gpio_oe (state set by GPIO_OEREG) */
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| SGPIO_OUT_MUX_CFG_P_OUT_CFG(0) /* 0x0 dout_doutm1 (1-bit mode) */
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;
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SGPIO_OUT_MUX_CFG( 9) = // SGPIO9: Input: qualifier
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SGPIO_OUT_MUX_CFG_P_OE_CFG(0) /* 0x0 gpio_oe (state set by GPIO_OEREG) */
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| SGPIO_OUT_MUX_CFG_P_OUT_CFG(0) /* 0x0 dout_doutm1 (1-bit mode) */
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;
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SGPIO_OUT_MUX_CFG(10) = // GPIO10: Output: disable
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SGPIO_OUT_MUX_CFG_P_OE_CFG(0) /* 0x0 gpio_oe (state set by GPIO_OEREG) */
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| SGPIO_OUT_MUX_CFG_P_OUT_CFG(4) /* 0x4=gpio_out (level set by GPIO_OUTREG) */
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;
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SGPIO_OUT_MUX_CFG(11) = // GPIO11: Output: direction
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SGPIO_OUT_MUX_CFG_P_OE_CFG(0) /* 0x0 gpio_oe (state set by GPIO_OEREG) */
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| SGPIO_OUT_MUX_CFG_P_OUT_CFG(4) /* 0x4=gpio_out (level set by GPIO_OUTREG) */
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;
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SGPIO_OUT_MUX_CFG(14) = // SGPIO14: Output: internal GPDMA burst request
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SGPIO_OUT_MUX_CFG_P_OE_CFG(0) /* 0x4 dout_oem1 (1-bit mode) */
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| SGPIO_OUT_MUX_CFG_P_OUT_CFG(0) /* 0x0 dout_doutm1 (1-bit mode) */
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;
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const uint_fast8_t output_multiplexing_mode =
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config->slice_mode_multislice ? 11 : 9;
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/* SGPIO0 to SGPIO7 */
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for(uint_fast8_t i=0; i<8; i++) {
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// SGPIO pin 0 outputs slice A bit "i".
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SGPIO_OUT_MUX_CFG(i) =
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SGPIO_OUT_MUX_CFG_P_OE_CFG(0)
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| SGPIO_OUT_MUX_CFG_P_OUT_CFG(output_multiplexing_mode) /* 11/0xB=dout_doutm8c (8-bit mode 8c)(multislice L0/7, N0/7), 9=dout_doutm8a (8-bit mode 8a)(A0/7,B0/7) */
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;
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}
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const uint_fast8_t slice_indices[] = {
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SGPIO_SLICE_A,
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SGPIO_SLICE_I,
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SGPIO_SLICE_E,
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SGPIO_SLICE_J,
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SGPIO_SLICE_C,
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SGPIO_SLICE_K,
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SGPIO_SLICE_F,
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SGPIO_SLICE_L,
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};
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const uint_fast8_t slice_gpdma = SGPIO_SLICE_H;
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const uint_fast8_t pos = config->slice_mode_multislice ? 0x1f : 0x03;
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const bool single_slice = !config->slice_mode_multislice;
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const uint_fast8_t slice_count = config->slice_mode_multislice ? 8 : 1;
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const uint_fast8_t clk_capture_mode = (direction == SGPIO_DIRECTION_TX) ? 0 : 0;
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uint32_t slice_enable_mask = 0;
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/* Configure Slice A, I, E, J, C, K, F, L (sgpio_slice_mode_multislice mode) */
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for(uint_fast8_t i=0; i<slice_count; i++)
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{
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const uint_fast8_t slice_index = slice_indices[i];
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const bool input_slice = (i == 0) && (direction != SGPIO_DIRECTION_TX); /* Only for slice0/A and RX mode set input_slice to 1 */
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const uint_fast8_t concat_order = (input_slice || single_slice) ? 0 : 3; /* 0x0=Self-loop(slice0/A RX mode), 0x3=8 slices */
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const uint_fast8_t concat_enable = (input_slice || single_slice) ? 0 : 1; /* 0x0=External data pin(slice0/A RX mode), 0x1=Concatenate data */
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SGPIO_MUX_CFG(slice_index) =
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SGPIO_MUX_CFG_CONCAT_ORDER(concat_order)
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| SGPIO_MUX_CFG_CONCAT_ENABLE(concat_enable)
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| SGPIO_MUX_CFG_QUALIFIER_SLICE_MODE(0) /* Select qualifier slice A(0x0) */
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| SGPIO_MUX_CFG_QUALIFIER_PIN_MODE(1) /* Select qualifier pin SGPIO9(0x1) */
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| SGPIO_MUX_CFG_QUALIFIER_MODE(3) /* External SGPIO */
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| SGPIO_MUX_CFG_CLK_SOURCE_SLICE_MODE(0) /* Select clock source slice D(0x0) */
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| SGPIO_MUX_CFG_CLK_SOURCE_PIN_MODE(0) /* Source Clock Pin 0x0 = SGPIO8 */
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| SGPIO_MUX_CFG_EXT_CLK_ENABLE(1) /* External clock signal(pin) selected */
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;
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SGPIO_SLICE_MUX_CFG(slice_index) =
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SGPIO_SLICE_MUX_CFG_INV_QUALIFIER(0) /* 0x0=Use normal qualifier. */
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| SGPIO_SLICE_MUX_CFG_PARALLEL_MODE(3) /* 0x3=Shift 1 byte(8bits) per clock. */
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| SGPIO_SLICE_MUX_CFG_DATA_CAPTURE_MODE(0) /* 0x0=Detect rising edge. (Condition for input bit match interrupt) */
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| SGPIO_SLICE_MUX_CFG_INV_OUT_CLK(0) /* 0x0=Normal clock. */
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| SGPIO_SLICE_MUX_CFG_CLKGEN_MODE(1) /* 0x1=Use external clock from a pin or other slice */
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| SGPIO_SLICE_MUX_CFG_CLK_CAPTURE_MODE(clk_capture_mode) /* 0x0=Use rising clock edge, 0x1=Use falling clock edge */
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| SGPIO_SLICE_MUX_CFG_MATCH_MODE(0) /* 0x0=Do not match data */
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;
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SGPIO_PRESET(slice_index) = 0; // External clock, don't care
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SGPIO_COUNT(slice_index) = 0; // External clock, don't care
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SGPIO_POS(slice_index) =
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SGPIO_POS_POS_RESET(pos)
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| SGPIO_POS_POS(pos)
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;
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SGPIO_REG(slice_index) = 0x00000000; // Primary output data register
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SGPIO_REG_SS(slice_index) = 0x00000000; // Shadow output data register
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slice_enable_mask |= (1 << slice_index);
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}
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if( config->slice_mode_multislice == false ) {
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SGPIO_MUX_CFG(slice_gpdma) =
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SGPIO_MUX_CFG_CONCAT_ORDER(0) /* Self-loop */
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| SGPIO_MUX_CFG_CONCAT_ENABLE(1)
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| SGPIO_MUX_CFG_QUALIFIER_SLICE_MODE(0) /* Select qualifier slice A(0x0) */
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| SGPIO_MUX_CFG_QUALIFIER_PIN_MODE(1) /* Select qualifier pin SGPIO9(0x1) */
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| SGPIO_MUX_CFG_QUALIFIER_MODE(3) /* External SGPIO */
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| SGPIO_MUX_CFG_CLK_SOURCE_SLICE_MODE(0) /* Select clock source slice D(0x0) */
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| SGPIO_MUX_CFG_CLK_SOURCE_PIN_MODE(0) /* Source Clock Pin 0x0 = SGPIO8 */
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| SGPIO_MUX_CFG_EXT_CLK_ENABLE(1) /* External clock signal(pin) selected */
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;
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SGPIO_SLICE_MUX_CFG(slice_gpdma) =
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SGPIO_SLICE_MUX_CFG_INV_QUALIFIER(0) /* 0x0=Use normal qualifier. */
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| SGPIO_SLICE_MUX_CFG_PARALLEL_MODE(0) /* 0x0=Shift 1 bit per clock. */
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| SGPIO_SLICE_MUX_CFG_DATA_CAPTURE_MODE(0) /* 0x0=Detect rising edge. (Condition for input bit match interrupt) */
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| SGPIO_SLICE_MUX_CFG_INV_OUT_CLK(0) /* 0x0=Normal clock. */
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| SGPIO_SLICE_MUX_CFG_CLKGEN_MODE(1) /* 0x1=Use external clock from a pin or other slice */
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| SGPIO_SLICE_MUX_CFG_CLK_CAPTURE_MODE(clk_capture_mode) /* 0x0=Use rising clock edge, 0x1=Use falling clock edge */
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| SGPIO_SLICE_MUX_CFG_MATCH_MODE(0) /* 0x0=Do not match data */
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;
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SGPIO_PRESET(slice_gpdma) = 0; // External clock, don't care
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SGPIO_COUNT(slice_gpdma) = 0; // External clock, don't care
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SGPIO_POS(slice_gpdma) =
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SGPIO_POS_POS_RESET(0x1f)
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| SGPIO_POS_POS(0x1f)
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;
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SGPIO_REG(slice_gpdma) = 0x11111111; // Primary output data register, LSB -> out
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SGPIO_REG_SS(slice_gpdma) = 0x11111111; // Shadow output data register, LSB -> out1
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slice_enable_mask |= (1 << slice_gpdma);
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}
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// Start SGPIO operation by enabling slice clocks.
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SGPIO_CTRL_ENABLE = slice_enable_mask;
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}
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void sgpio_cpld_stream_enable(sgpio_config_t* const config) {
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(void)config;
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// Enable codec data stream.
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SGPIO_GPIO_OUTREG &= ~(1L << 10); /* SGPIO10 */
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}
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void sgpio_cpld_stream_disable(sgpio_config_t* const config) {
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(void)config;
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// Disable codec data stream.
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SGPIO_GPIO_OUTREG |= (1L << 10); /* SGPIO10 */
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}
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bool sgpio_cpld_stream_is_enabled(sgpio_config_t* const config) {
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(void)config;
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return (SGPIO_GPIO_OUTREG & (1L << 10)) == 0; /* SGPIO10 */
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}
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#ifdef RAD1O
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/* The rad1o hardware has a bug which makes it
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* necessary to also switch between the two options based
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* on TX or RX mode.
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*
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* We use the state of the pin to determine which way we
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* have to go.
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*
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* As TX/RX can change without sgpio_cpld_stream_rx_set_q_invert
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* being called, we store a local copy of its parameter. */
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static bool sgpio_invert = false;
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/* Called when TX/RX changes od sgpio_cpld_stream_rx_set_q_invert
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* gets called. */
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static void update_q_invert(sgpio_config_t* const config) {
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/* 1=Output SGPIO11 High(TX mode), 0=Output SGPIO11 Low(RX mode) */
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bool tx_mode = (SGPIO_GPIO_OUTREG & (1 << 11)) > 0;
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/* 0.13: P1_18 */
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if( !sgpio_invert & !tx_mode) {
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gpio_write(config->gpio_rx_q_invert, 1);
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} else if( !sgpio_invert & tx_mode) {
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gpio_write(config->gpio_rx_q_invert, 0);
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} else if( sgpio_invert & !tx_mode) {
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gpio_write(config->gpio_rx_q_invert, 0);
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} else if( sgpio_invert & tx_mode) {
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gpio_write(config->gpio_rx_q_invert, 1);
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}
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}
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void sgpio_cpld_stream_rx_set_q_invert(sgpio_config_t* const config, const uint_fast8_t invert) {
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if( invert ) {
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sgpio_invert = true;
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} else {
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sgpio_invert = false;
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}
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update_q_invert(config);
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}
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#else
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void sgpio_cpld_stream_rx_set_q_invert(sgpio_config_t* const config, const uint_fast8_t invert) {
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gpio_write(config->gpio_rx_q_invert, invert);
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}
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#endif
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