9a53fd3a07
Change Si5351C CLK2 to 10MHz. Keep CLK3 at 20MHz, but not inverted. Source SGPIO8 from P1_12 instead of P9_6. (See "SGPIO Clock Routing") modification at https://github.com/mossmann/hackrf/wiki/Future-Hardware-Modifications ).
CPLD interface between LPC43xx microcontroller SGPIO peripheral and MAX5864 RF codec.
Requirements
To build this VHDL project and produce an SVF file for flashing the CPLD:
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Xilinx WebPACK 13.4 for Windows or Linux.
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BSDL model files for Xilinx CoolRunner-II XC264A, available at xilinx.com, in the "Device Models" Support Resources section of the CoolRunner-II Product Support & Documentation page. Only one file from the BSDL package is required, and the "program" script below expects it to be at the relative path "bsdl/xc2c/xc2c64.bsd".
To program the SVF file into the CPLD:
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Dangerous Prototypes Bus Blaster v2:
- Configured with JTAGKey buffers.
- Connected to CPLD JTAG signals on Jellybean.
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urJTAG built with libftdi support.
To Program
./program
...which connects to the Bus Blaster interface 0, sets the BSDL directory, detects devices on the JTAG chain, and writes the sgpio_if.svf file to the CPLD.