380 lines
14 KiB
C
380 lines
14 KiB
C
/*
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* Copyright 2012 Jared Boone <jared@sharebrained.com>
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*
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* This file is part of HackRF.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 51 Franklin Street,
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* Boston, MA 02110-1301, USA.
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*/
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#include <libopencm3/lpc43xx/scu.h>
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#include <libopencm3/lpc43xx/sgpio.h>
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#include <hackrf_core.h>
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void sgpio_configure_pin_functions() {
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scu_pinmux(SCU_PINMUX_SGPIO0, SCU_GPIO_FAST | SCU_CONF_FUNCTION3);
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scu_pinmux(SCU_PINMUX_SGPIO1, SCU_GPIO_FAST | SCU_CONF_FUNCTION3);
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scu_pinmux(SCU_PINMUX_SGPIO2, SCU_GPIO_FAST | SCU_CONF_FUNCTION2);
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scu_pinmux(SCU_PINMUX_SGPIO3, SCU_GPIO_FAST | SCU_CONF_FUNCTION2);
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scu_pinmux(SCU_PINMUX_SGPIO4, SCU_GPIO_FAST | SCU_CONF_FUNCTION2);
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scu_pinmux(SCU_PINMUX_SGPIO5, SCU_GPIO_FAST | SCU_CONF_FUNCTION2);
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scu_pinmux(SCU_PINMUX_SGPIO6, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
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scu_pinmux(SCU_PINMUX_SGPIO7, SCU_GPIO_FAST | SCU_CONF_FUNCTION6);
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scu_pinmux(SCU_PINMUX_SGPIO8, SCU_GPIO_FAST | SCU_CONF_FUNCTION6);
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scu_pinmux(SCU_PINMUX_SGPIO9, SCU_GPIO_FAST | SCU_CONF_FUNCTION7);
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scu_pinmux(SCU_PINMUX_SGPIO10, SCU_GPIO_FAST | SCU_CONF_FUNCTION6);
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scu_pinmux(SCU_PINMUX_SGPIO11, SCU_GPIO_FAST | SCU_CONF_FUNCTION6);
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scu_pinmux(SCU_PINMUX_SGPIO12, SCU_GPIO_FAST | SCU_CONF_FUNCTION6);
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scu_pinmux(SCU_PINMUX_SGPIO13, SCU_GPIO_FAST | SCU_CONF_FUNCTION7);
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scu_pinmux(SCU_PINMUX_SGPIO14, SCU_GPIO_FAST | SCU_CONF_FUNCTION7);
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scu_pinmux(SCU_PINMUX_SGPIO15, SCU_GPIO_FAST | SCU_CONF_FUNCTION7);
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}
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void sgpio_test_interface() {
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const uint_fast8_t host_clock_sgpio_pin = 8; // Input
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const uint_fast8_t host_capture_sgpio_pin = 9; // Input
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const uint_fast8_t host_disable_sgpio_pin = 10; // Output
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const uint_fast8_t host_direction_sgpio_pin = 11; // Output
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SGPIO_GPIO_OENREG = 0; // All inputs for the moment.
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// Disable all counters during configuration
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SGPIO_CTRL_ENABLE = 0;
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sgpio_configure_pin_functions();
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// Make all SGPIO controlled by SGPIO's "GPIO" registers
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for (uint_fast8_t i = 0; i < 16; i++) {
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SGPIO_OUT_MUX_CFG(i) = (0L << 4) | (4L << 0);
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}
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// Set SGPIO output values.
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SGPIO_GPIO_OUTREG = (1L << host_direction_sgpio_pin)
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| (1L << host_disable_sgpio_pin);
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// Enable SGPIO pin outputs.
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SGPIO_GPIO_OENREG = (1L << host_direction_sgpio_pin)
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| (1L << host_disable_sgpio_pin) | (0L << host_capture_sgpio_pin)
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| (0L << host_clock_sgpio_pin) | (0xFF << 0);
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// Configure SGPIO slices.
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// Enable codec data stream.
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SGPIO_GPIO_OUTREG &= ~(1L << host_disable_sgpio_pin);
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while (1) {
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for (uint_fast8_t i = 0; i < 8; i++) {
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SGPIO_GPIO_OUTREG ^= (1L << i);
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}
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}
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}
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void sgpio_configure_for_tx() {
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// Disable all counters during configuration
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SGPIO_CTRL_ENABLE = 0;
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sgpio_configure_pin_functions();
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// Set SGPIO output values.
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SGPIO_GPIO_OUTREG =
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(1L << 11) | // direction
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(1L << 10); // disable
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// Enable SGPIO pin outputs.
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SGPIO_GPIO_OENREG =
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(1L << 11) | // direction: TX: data to CPLD
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(1L << 10) | // disable
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(0L << 9) | // capture
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(0L << 8) | // clock
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0xFF; // data: output
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SGPIO_OUT_MUX_CFG( 8) = 0; // SGPIO: Input: clock
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SGPIO_OUT_MUX_CFG( 9) = 0; // SGPIO: Input: qualifier
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SGPIO_OUT_MUX_CFG(10) = (0L << 4) | (4L << 0); // GPIO: Output: disable
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SGPIO_OUT_MUX_CFG(11) = (0L << 4) | (4L << 0); // GPIO: Output: direction
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for(uint_fast8_t i=0; i<8; i++) {
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// SGPIO pin 0 outputs slice A bit "i".
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SGPIO_OUT_MUX_CFG(i) =
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(0L << 4) | // P_OE_CFG = 0
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(9L << 0); // P_OUT_CFG = 9, dout_doutm8a (8-bit mode 8a)
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}
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// Slice A
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SGPIO_MUX_CFG(SGPIO_SLICE_A) =
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(0L << 12) | // CONCAT_ORDER = 0 (self-loop)
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(1L << 11) | // CONCAT_ENABLE = 1 (concatenate data)
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(0L << 9) | // QUALIFIER_SLICE_MODE = X
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(1L << 7) | // QUALIFIER_PIN_MODE = 1 (SGPIO9)
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(3L << 5) | // QUALIFIER_MODE = 3 (external SGPIO pin)
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(0L << 3) | // CLK_SOURCE_SLICE_MODE = X
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(0L << 1) | // CLK_SOURCE_PIN_MODE = 0 (SGPIO8)
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(1L << 0); // EXT_CLK_ENABLE = 1, external clock signal (slice)
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SGPIO_SLICE_MUX_CFG(SGPIO_SLICE_A) =
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(0L << 8) | // INV_QUALIFIER = 0 (use normal qualifier)
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(3L << 6) | // PARALLEL_MODE = 3 (shift 8 bits per clock)
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(0L << 4) | // DATA_CAPTURE_MODE = 0 (detect rising edge)
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(0L << 3) | // INV_OUT_CLK = 0 (normal clock)
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(1L << 2) | // CLKGEN_MODE = 1 (use external pin clock)
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(0L << 1) | // CLK_CAPTURE_MODE = 0 (use rising clock edge)
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(0L << 0); // MATCH_MODE = 0 (do not match data)
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SGPIO_PRESET(SGPIO_SLICE_A) = 0;
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SGPIO_COUNT(SGPIO_SLICE_A) = 0;
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SGPIO_POS(SGPIO_SLICE_A) = (0x3L << 8) | (0x3L << 0);
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SGPIO_REG(SGPIO_SLICE_A) = 0x80808080; // Primary output data register
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SGPIO_REG_SS(SGPIO_SLICE_A) = 0x80808080; // Shadow output data register
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// Start SGPIO operation by enabling slice clocks.
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SGPIO_CTRL_ENABLE =
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(1L << SGPIO_SLICE_A)
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;
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}
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void sgpio_configure_for_tx_deep() {
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// Disable all counters during configuration
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SGPIO_CTRL_ENABLE = 0;
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sgpio_configure_pin_functions();
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// Set SGPIO output values.
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SGPIO_GPIO_OUTREG =
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(1L << 11) | // direction
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(1L << 10); // disable
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// Enable SGPIO pin outputs.
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SGPIO_GPIO_OENREG =
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(1L << 11) | // direction: TX: data to CPLD
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(1L << 10) | // disable
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(0L << 9) | // capture
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(0L << 8) | // clock
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0xFF; // data: output
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SGPIO_OUT_MUX_CFG( 8) = 0; // SGPIO: Input: clock
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SGPIO_OUT_MUX_CFG( 9) = 0; // SGPIO: Input: qualifier
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SGPIO_OUT_MUX_CFG(10) = (0L << 4) | (4L << 0); // GPIO: Output: disable
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SGPIO_OUT_MUX_CFG(11) = (0L << 4) | (4L << 0); // GPIO: Output: direction
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for(uint_fast8_t i=0; i<8; i++) {
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// SGPIO pin 0 outputs slice A bit "i".
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SGPIO_OUT_MUX_CFG(i) =
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(0L << 4) | // P_OE_CFG = 0
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(11L << 0); // P_OUT_CFG = 11, dout_doutm8c (8-bit mode 8c)
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}
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const uint_fast8_t slice_indices[] = {
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SGPIO_SLICE_A,
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SGPIO_SLICE_I,
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SGPIO_SLICE_E,
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SGPIO_SLICE_J,
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SGPIO_SLICE_C,
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SGPIO_SLICE_K,
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SGPIO_SLICE_F,
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SGPIO_SLICE_L,
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};
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uint32_t slice_enable_mask = 0;
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for(uint_fast8_t i=0; i<8; i++) {
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uint_fast8_t slice_index = slice_indices[i];
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const uint_fast8_t concat_order = 3;
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const uint_fast8_t concat_enable = 1;
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SGPIO_MUX_CFG(slice_index) =
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(concat_order << 12) | // CONCAT_ORDER = 3 (eight slices)
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(concat_enable << 11) | // CONCAT_ENABLE = 1 (concatenate data)
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(0L << 9) | // QUALIFIER_SLICE_MODE = X
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(1L << 7) | // QUALIFIER_PIN_MODE = 1 (SGPIO9)
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(3L << 5) | // QUALIFIER_MODE = 3 (external SGPIO pin)
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(0L << 3) | // CLK_SOURCE_SLICE_MODE = X
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(0L << 1) | // CLK_SOURCE_PIN_MODE = 0 (SGPIO8)
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(1L << 0); // EXT_CLK_ENABLE = 1, external clock signal (slice)
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SGPIO_SLICE_MUX_CFG(slice_index) =
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(0L << 8) | // INV_QUALIFIER = 0 (use normal qualifier)
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(3L << 6) | // PARALLEL_MODE = 3 (shift 8 bits per clock)
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(0L << 4) | // DATA_CAPTURE_MODE = 0 (detect rising edge)
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(0L << 3) | // INV_OUT_CLK = X
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(1L << 2) | // CLKGEN_MODE = 1 (use external pin clock)
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(1L << 1) | // CLK_CAPTURE_MODE = 1 (use falling clock edge)
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(0L << 0); // MATCH_MODE = 0 (do not match data)
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SGPIO_PRESET(slice_index) = 0; // External clock, don't care
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SGPIO_COUNT(slice_index) = 0; // External clock, don't care
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SGPIO_POS(slice_index) = (0x1f << 8) | (0x1f << 0);
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SGPIO_REG(slice_index) = 0xFFFFFFFF; // Primary output data register
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SGPIO_REG_SS(slice_index) = 0xFFFFFFFF; // Shadow output data register
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slice_enable_mask |= (1 << slice_index);
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}
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// Start SGPIO operation by enabling slice clocks.
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SGPIO_CTRL_ENABLE = slice_enable_mask;
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}
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void sgpio_configure_for_rx() {
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// Disable all counters during configuration
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SGPIO_CTRL_ENABLE = 0;
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sgpio_configure_pin_functions();
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// Set SGPIO output values.
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SGPIO_GPIO_OUTREG =
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(0L << 11) | // direction
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(1L << 10); // disable
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// Enable SGPIO pin outputs.
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SGPIO_GPIO_OENREG =
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(1L << 11) | // direction: RX: data from CPLD
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(1L << 10) | // disable
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(0L << 9) | // capture
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(0L << 8) | // clock
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0x00; // data: input
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SGPIO_OUT_MUX_CFG( 8) = 0; // SGPIO: Input: clock
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SGPIO_OUT_MUX_CFG( 9) = 0; // SGPIO: Input: qualifier
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SGPIO_OUT_MUX_CFG(10) = (0L << 4) | (4L << 0); // GPIO: Output: disable
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SGPIO_OUT_MUX_CFG(11) = (0L << 4) | (4L << 0); // GPIO: Output: direction
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for(uint_fast8_t i=0; i<8; i++) {
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SGPIO_OUT_MUX_CFG(i) =
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(0L << 4) | // P_OE_CFG = 0
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(9L << 0); // P_OUT_CFG = 9, dout_doutm8a (8-bit mode 8a)
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}
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// Slice A
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SGPIO_MUX_CFG(SGPIO_SLICE_A) =
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(0L << 12) | // CONCAT_ORDER = X
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(0L << 11) | // CONCAT_ENABLE = 0 (concatenate data)
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(0L << 9) | // QUALIFIER_SLICE_MODE = X
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(1L << 7) | // QUALIFIER_PIN_MODE = 1 (SGPIO9)
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(3L << 5) | // QUALIFIER_MODE = 3 (external SGPIO pin)
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(0L << 3) | // CLK_SOURCE_SLICE_MODE = X
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(0L << 1) | // CLK_SOURCE_PIN_MODE = 0 (SGPIO8)
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(1L << 0); // EXT_CLK_ENABLE = 1, external clock signal (slice)
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SGPIO_SLICE_MUX_CFG(SGPIO_SLICE_A) =
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(0L << 8) | // INV_QUALIFIER = 0 (use normal qualifier)
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(3L << 6) | // PARALLEL_MODE = 3 (shift 8 bits per clock)
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(0L << 4) | // DATA_CAPTURE_MODE = 0 (detect rising edge)
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(0L << 3) | // INV_OUT_CLK = X
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(1L << 2) | // CLKGEN_MODE = 1 (use external pin clock)
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(1L << 1) | // CLK_CAPTURE_MODE = 1 (use falling clock edge)
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(0L << 0); // MATCH_MODE = 0 (do not match data)
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SGPIO_PRESET(SGPIO_SLICE_A) = 0;
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SGPIO_COUNT(SGPIO_SLICE_A) = 0;
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SGPIO_POS(SGPIO_SLICE_A) = (0 << 8) | (0 << 0);
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SGPIO_REG(SGPIO_SLICE_A) = 0xCAFEBABE; // Primary output data register
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SGPIO_REG_SS(SGPIO_SLICE_A) = 0xDEADBEEF; // Shadow output data register
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// Start SGPIO operation by enabling slice clocks.
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SGPIO_CTRL_ENABLE =
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(1L << SGPIO_SLICE_A)
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;
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}
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void sgpio_configure_for_rx_deep() {
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// Disable all counters during configuration
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SGPIO_CTRL_ENABLE = 0;
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sgpio_configure_pin_functions();
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// Set SGPIO output values.
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SGPIO_GPIO_OUTREG =
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(0L << 11) | // direction
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(1L << 10); // disable
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// Enable SGPIO pin outputs.
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SGPIO_GPIO_OENREG =
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(1L << 11) | // direction: RX: data from CPLD
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(1L << 10) | // disable
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(0L << 9) | // capture
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(0L << 8) | // clock
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0x00; // data: input
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SGPIO_OUT_MUX_CFG( 8) = 0; // SGPIO: Input: clock
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SGPIO_OUT_MUX_CFG( 9) = 0; // SGPIO: Input: qualifier
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SGPIO_OUT_MUX_CFG(10) = (0L << 4) | (4L << 0); // GPIO: Output: disable
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SGPIO_OUT_MUX_CFG(11) = (0L << 4) | (4L << 0); // GPIO: Output: direction
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for(uint_fast8_t i=0; i<8; i++) {
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SGPIO_OUT_MUX_CFG(i) =
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(0L << 4) | // P_OE_CFG = 0
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(9L << 0); // P_OUT_CFG = 9, dout_doutm8a (8-bit mode 8a)
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}
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const uint_fast8_t slice_indices[] = {
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SGPIO_SLICE_A,
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SGPIO_SLICE_I,
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SGPIO_SLICE_E,
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SGPIO_SLICE_J,
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SGPIO_SLICE_C,
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SGPIO_SLICE_K,
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SGPIO_SLICE_F,
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SGPIO_SLICE_L,
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};
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uint32_t slice_enable_mask = 0;
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for(uint_fast8_t i=0; i<8; i++) {
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uint_fast8_t slice_index = slice_indices[i];
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const uint_fast8_t concat_order = (slice_index == SGPIO_SLICE_A) ? 0 : 3;
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const uint_fast8_t concat_enable = (slice_index == SGPIO_SLICE_A) ? 0 : 1;
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SGPIO_MUX_CFG(slice_index) =
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(concat_order << 12) | // CONCAT_ORDER = 3 (eight slices)
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(concat_enable << 11) | // CONCAT_ENABLE = 1 (concatenate data)
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(0L << 9) | // QUALIFIER_SLICE_MODE = X
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(1L << 7) | // QUALIFIER_PIN_MODE = 1 (SGPIO9)
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(3L << 5) | // QUALIFIER_MODE = 3 (external SGPIO pin)
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(0L << 3) | // CLK_SOURCE_SLICE_MODE = X
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(0L << 1) | // CLK_SOURCE_PIN_MODE = 0 (SGPIO8)
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(1L << 0); // EXT_CLK_ENABLE = 1, external clock signal (slice)
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SGPIO_SLICE_MUX_CFG(slice_index) =
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(0L << 8) | // INV_QUALIFIER = 0 (use normal qualifier)
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(3L << 6) | // PARALLEL_MODE = 3 (shift 8 bits per clock)
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(0L << 4) | // DATA_CAPTURE_MODE = 0 (detect rising edge)
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(0L << 3) | // INV_OUT_CLK = X
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(1L << 2) | // CLKGEN_MODE = 1 (use external pin clock)
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(1L << 1) | // CLK_CAPTURE_MODE = 1 (use falling clock edge)
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(0L << 0); // MATCH_MODE = 0 (do not match data)
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SGPIO_PRESET(slice_index) = 0; // External clock, don't care
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SGPIO_COUNT(slice_index) = 0; // External clock, don't care
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SGPIO_POS(slice_index) = (0x1f << 8) | (0x1f << 0);
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SGPIO_REG(slice_index) = 0xFFFFFFFF; // Primary output data register
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SGPIO_REG_SS(slice_index) = 0xFFFFFFFF; // Shadow output data register
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slice_enable_mask |= (1 << slice_index);
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}
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// Start SGPIO operation by enabling slice clocks.
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SGPIO_CTRL_ENABLE = slice_enable_mask;
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}
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void sgpio_cpld_stream_enable() {
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// Enable codec data stream.
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SGPIO_GPIO_OUTREG &= ~(1L << 10);
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}
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void sgpio_cpld_stream_disable() {
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// Disable codec data stream.
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SGPIO_GPIO_OUTREG |= (1L << 10);
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}
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bool sgpio_cpld_stream_is_enabled() {
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return (SGPIO_GPIO_OUTREG & (1L << 10)) == 0;
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} |