533f9ee332
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This commit allows to synchronise multiple HackRFs with a synchronisation error **below 1 sampling period**
> WARNING: Use this at your own risk. If you don't know what you are doing you may damage your HackRF.
> The author takes no responsability for potential damages
Usage example: synchronise two HackRFs
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1. Chose the master HackRF which will send the synchronisation pulse (HackRF0). HackRF1 will represent the slave hackrf.
2. Retreive the serial number of both HackRFs using `hackrf_info`
3. Use a wire to connect `SYNC_CMD` of HackRF0 to `SYNC_IN` of HackRF0 and HackRF1
4. Run `hackrf_transfer` with the argument `-H 1` to enable hardware synchronisation:
```
$ hackrf_tranfer ... -r rec1.bin -d HackRF1_serial -H 1 | hackrf_transfer ... -r rec0.bin -d HackRF0_serial -H 1
```
rec0.bin and rec1.bin will have a time offset below 1 sampling period.
The 1PPS output of GNSS receivers can be used to synchronise HackRFs even if they are far from each other.
>DON'T APPLY INCOMPATIBLE VOLTAGE LEVELS TO THE CPLD PINS
Signal | Header |Pin | Description
-------|--------|----|------------
`SYNC_IN` | P28 | 16 | Synchronisation pulse input
`SYNC_CMD` | P28 | 15 | Synchronisation pulse output
Note:
=====
I had to remove CPLD-based decimation to use a GPIO for enabling hardware.
More info:
==========
[M. Bartolucci, J. A. Del Peral-Rosado, R. Estatuet-Castillo, J. A. Garcia-Molina, M. Crisci and G. E. Corazza, "Synchronisation of low-cost open source SDRs for navigation applications," 2016 8th ESA Workshop on Satellite Navigation Technologies and European Workshop on GNSS Signals and Signal Processing (NAVITEC), Noordwijk, 2016, pp. 1-7.](http://ieeexplore.ieee.org/document/7849328/)
[Alternative link](http://spcomnav.uab.es/docs/conferences/Bartolucci_NAVITEC_2016.pdf)
73 lines
3.4 KiB
Plaintext
Executable File
73 lines
3.4 KiB
Plaintext
Executable File
#
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# Copyright 2012 Jared Boone
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#
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# This file is part of HackRF.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 2, or (at your option)
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# any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; see the file COPYING. If not, write to
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# the Free Software Foundation, Inc., 51 Franklin Street,
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# Boston, MA 02110-1301, USA.
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NET "CODEC_X2_CLK" TNM_NET = CODEC_X2_CLK;
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TIMESPEC TS_codec_x2_data = PERIOD "CODEC_X2_CLK" 25 ns;
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TIMEGRP "adc_data" OFFSET = IN 16 ns BEFORE "CODEC_X2_CLK";
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TIMEGRP "dac_data" OFFSET = OUT 15 ns AFTER "CODEC_X2_CLK";
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TIMEGRP "to_host" OFFSET = OUT 20 ns AFTER "CODEC_X2_CLK";
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#PACE: Start of Constraints generated by PACE
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#PACE: Start of PACE I/O Pin Assignments
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NET "CODEC_CLK" LOC = "P23" | IOSTANDARD = LVCMOS33 ;
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NET "CODEC_X2_CLK" LOC = "P27" | IOSTANDARD = LVCMOS33 ;
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NET "DA<0>" LOC = "P43" | IOSTANDARD = LVCMOS33 ;
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NET "DA<1>" LOC = "P42" | IOSTANDARD = LVCMOS33 ;
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NET "DA<2>" LOC = "P41" | IOSTANDARD = LVCMOS33 ;
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NET "DA<3>" LOC = "P40" | IOSTANDARD = LVCMOS33 ;
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NET "DA<4>" LOC = "P39" | IOSTANDARD = LVCMOS33 ;
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NET "DA<5>" LOC = "P37" | IOSTANDARD = LVCMOS33 ;
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NET "DA<6>" LOC = "P36" | IOSTANDARD = LVCMOS33 ;
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NET "DA<7>" LOC = "P35" | IOSTANDARD = LVCMOS33 ;
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NET "DD<0>" LOC = "P34" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
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NET "DD<1>" LOC = "P33" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
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NET "DD<2>" LOC = "P32" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
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NET "DD<3>" LOC = "P30" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
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NET "DD<4>" LOC = "P29" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
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NET "DD<5>" LOC = "P28" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
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NET "DD<6>" LOC = "P24" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
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NET "DD<7>" LOC = "P19" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
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NET "DD<8>" LOC = "P18" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
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NET "DD<9>" LOC = "P17" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
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NET "HOST_CAPTURE" LOC = "P91" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
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NET "HOST_DATA<0>" LOC = "P89" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
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NET "HOST_DATA<1>" LOC = "P79" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
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NET "HOST_DATA<2>" LOC = "P74" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
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NET "HOST_DATA<3>" LOC = "P72" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
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NET "HOST_DATA<4>" LOC = "P67" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
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NET "HOST_DATA<5>" LOC = "P64" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
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NET "HOST_DATA<6>" LOC = "P61" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
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NET "HOST_DATA<7>" LOC = "P77" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
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NET "HOST_DIRECTION" LOC = "P71" | IOSTANDARD = LVCMOS33 ;
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NET "HOST_DISABLE" LOC = "P76" | IOSTANDARD = LVCMOS33 ;
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NET "HOST_Q_INVERT" LOC = "P70" | IOSTANDARD = LVCMOS33 ;
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NET "HOST_SYNC_EN" LOC = "P90" | IOSTANDARD = LVCMOS33 ;
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NET "HOST_SYNC" LOC = "P55" | IOSTANDARD = LVCMOS33;
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NET "HOST_SYNC_CMD" LOC = "P56" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
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#PACE: Start of PACE Area Constraints
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#PACE: Start of PACE Prohibit Constraints
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#PACE: End of Constraints generated by PACE
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