Jared Boone d103c31187 CPLD: Rework timing between ADC, CPLD, SGPIO
Capture ADC and codec clock state with sufficient timing margin.
Increase drive strength on codec clock and invert CPLD capture clock to provide margin for capturing codec clock (I vs. Q channel).
2019-01-18 16:09:14 -08:00
..
2015-07-22 22:56:17 +02:00
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2017-01-27 20:45:49 +01:00
2016-12-27 21:08:12 +00:00
2017-05-16 11:39:44 +02:00

This directory contains things shared by multiple HackRF firmware
implementations.