132 lines
3.5 KiB
VHDL
Executable File
132 lines
3.5 KiB
VHDL
Executable File
--
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-- Copyright 2012 Jared Boone
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--
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-- This file is part of HackRF.
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2, or (at your option)
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-- any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; see the file COPYING. If not, write to
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-- the Free Software Foundation, Inc., 51 Franklin Street,
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-- Boston, MA 02110-1301, USA.
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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ENTITY top_tb IS
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END top_tb;
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ARCHITECTURE behavior OF top_tb IS
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COMPONENT top
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PORT(
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HOST_DATA : INOUT std_logic_vector(7 downto 0);
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HOST_CAPTURE : OUT std_logic;
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HOST_DISABLE : IN std_logic;
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HOST_DIRECTION : IN std_logic;
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HOST_DECIM_SEL : IN std_logic_vector(2 downto 0);
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DA : IN std_logic_vector(7 downto 0);
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DD : OUT std_logic_vector(9 downto 0);
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CODEC_CLK : IN std_logic;
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CODEC_X2_CLK : IN std_logic
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);
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END COMPONENT;
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--Inputs
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signal DA : std_logic_vector(7 downto 0) := (others => '0');
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signal CODEC_CLK : std_logic := '0';
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signal CODEC_X2_CLK : std_logic := '0';
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signal HOST_DISABLE : std_logic := '1';
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signal HOST_DIRECTION : std_logic := '0';
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signal HOST_DECIM_SEL : std_logic_vector(2 downto 0) := "010";
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--BiDirs
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signal HOST_DATA : std_logic_vector(7 downto 0);
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--Outputs
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signal DD : std_logic_vector(9 downto 0);
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signal HOST_CAPTURE : std_logic;
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begin
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uut: top PORT MAP (
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HOST_DATA => HOST_DATA,
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HOST_CAPTURE => HOST_CAPTURE,
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HOST_DISABLE => HOST_DISABLE,
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HOST_DIRECTION => HOST_DIRECTION,
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HOST_DECIM_SEL => HOST_DECIM_SEL,
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DA => DA,
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DD => DD,
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CODEC_CLK => CODEC_CLK,
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CODEC_X2_CLK => CODEC_X2_CLK
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);
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clk_process :process
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begin
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CODEC_CLK <= '1';
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CODEC_X2_CLK <= '1';
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wait for 12.5 ns;
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CODEC_X2_CLK <= '0';
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wait for 12.5 ns;
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CODEC_CLK <= '0';
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CODEC_X2_CLK <= '1';
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wait for 12.5 ns;
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CODEC_X2_CLK <= '0';
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wait for 12.5 ns;
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end process;
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adc_proc: process
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begin
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wait until rising_edge(CODEC_CLK);
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wait for 9 ns;
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DA <= "00000000";
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wait until falling_edge(CODEC_CLK);
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wait for 9 ns;
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DA <= "00000001";
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end process;
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sgpio_proc: process
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begin
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HOST_DATA <= (others => 'Z');
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HOST_DIRECTION <= '0';
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HOST_DISABLE <= '1';
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wait for 135 ns;
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HOST_DISABLE <= '0';
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wait for 1000 ns;
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HOST_DISABLE <= '1';
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wait for 100 ns;
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HOST_DIRECTION <= '1';
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wait for 100 ns;
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HOST_DISABLE <= '0';
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for i in 0 to 10 loop
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HOST_DATA <= (others => '0');
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wait until rising_edge(CODEC_CLK) and HOST_CAPTURE = '1';
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HOST_DATA <= (others => '1');
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wait until rising_edge(CODEC_CLK) and HOST_CAPTURE = '1';
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end loop;
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wait;
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end process;
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end;
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