Marco Bartolucci
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fa6bde951c
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Added CPLD-based synchronization
This is a proof of concept and it's still very crude
For more info read (http://spcomnav.uab.es/docs/conferences/Bartolucci_NAVITEC_2016.pdf)
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2017-02-17 13:58:55 +01:00 |
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Jared Boone
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a380713fdd
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CPLD: Separate RX and TX invert, fix TX invert sense.
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2014-08-20 08:38:27 -07:00 |
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Jared Boone
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ad403fb370
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CPLD: Add TX Q invert mechanism.
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2014-08-16 17:15:13 -07:00 |
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Jared Boone
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8e387e5489
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CPLD: Update bitstream files with RX Q channel flip.
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2014-08-11 13:02:14 -07:00 |
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Jared Boone
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19f285288c
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Reset decimator sample count when host_data_enable is 0, so that sample stream starts with a consistent phase. May not be particularly important, but feels cleaner this way...
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2014-01-11 15:17:39 -08:00 |
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Jared Boone
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3bf6573dc6
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Add skip-every-N function to CPLD, where N is controlled by three input pins from the microcontroller.
Updated SGPIO CPLD testbench, as it had fallen a bit out of date.
Add SGPIO API initialization and control of CPLD decimation feature.
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2013-11-19 19:52:06 -08:00 |
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Jared Boone
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d006ec769c
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Updated CPLD bitstream with two's complement I/O and sample ordering fix.
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2013-11-16 13:41:54 -08:00 |
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Michael Ossmann
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9276b9e89a
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moved cpld stuff out of hardware/jellybean where people would be unlikely to look for it
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2013-05-18 09:48:37 -06:00 |
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