Michael Ossmann
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ebaccf46f4
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adjusted clock generator output drive strength
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2013-11-22 17:24:53 -07:00 |
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Michael Ossmann
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5b14636c2c
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initial firmware support for HackRF One
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2013-11-19 10:01:26 -07:00 |
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Hoernchen
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1e326997ed
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firmware: enable int mode if div is even integer
to improve jitter performance
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2013-06-07 23:10:35 +02:00 |
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Hoernchen
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1925649a01
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firmware: fractional sample rates
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2013-06-07 14:29:14 +02:00 |
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Hoernchen
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a95f49b543
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disable si clock to lpc
leaving it on but unused causes major spurs to appear all over the
place..
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2013-06-05 17:35:01 +02:00 |
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Hoernchen
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7f6a730c6e
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si clock for the lpc
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2013-05-29 17:12:06 +02:00 |
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Jared Boone
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4f9a5a1ba4
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Fix-ups to copyrights -- missing e-mail address and inconsistent formatting.
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2012-10-06 19:14:55 -07:00 |
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Michael Ossmann
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2c813ec41e
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Jawbreaker clock generator configuration
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2012-09-19 13:43:16 -06:00 |
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Michael Ossmann
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cbd2d98c7d
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fixed bad output spectrum. problem was P3 = 0 in si5351c pll, similar to commit b595de647077f208c534e4efc0bce92f25378fb8
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2012-08-22 10:41:53 -06:00 |
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Jared Boone
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9a53fd3a07
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New CPLD .svf.
Change Si5351C CLK2 to 10MHz.
Keep CLK3 at 20MHz, but not inverted.
Source SGPIO8 from P1_12 instead of P9_6. (See "SGPIO Clock Routing") modification at https://github.com/mossmann/hackrf/wiki/Future-Hardware-Modifications ).
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2012-06-15 16:12:35 -07:00 |
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Michael Ossmann
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ad080a355a
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pull request #10, resolved conflicts
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2012-06-13 21:21:34 -06:00 |
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Jared Boone
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02f61f4d64
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Added r_div argument to si5351c_configure_multisynth(). Modified Jellybean clock setup to provide 10MHz clock to MAX5864 and 20MHz to CPLD (both inverted and non-inverted).
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2012-06-13 17:53:10 -07:00 |
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Michael Ossmann
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056ddd0601
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r divider configurable, added CLK5 for mixer reference input
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2012-06-13 16:02:40 -06:00 |
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Michael Ossmann
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aeced361cf
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migrated common stuff to libopencm3
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2012-06-07 08:14:16 -06:00 |
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Michael Ossmann
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f01fc2d445
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initial port of Jared\'s initialization code to libopencm3, not complete yet
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2012-06-05 22:20:56 -06:00 |
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