496 Commits

Author SHA1 Message Date
Jared Boone
e05677ab0d OperaCake: Bring together with PortaPack code.
The plan is to have them coexist in the firmware binary, even if the hardware is mutually exclusive at runtime.
2019-01-07 15:35:41 -08:00
Jared Boone
46ba0512d4 PortaPack: Remove noisy, extraneous "+" for amplifier gain labels, add space before "dB". 2019-01-02 09:37:43 -08:00
Jared Boone
c477317408 PortaPack: Improve baseband filter frequency label readability. 2019-01-02 09:35:15 -08:00
Jared Boone
a2902d7d3a PortaPack: Hide first-IF mixer icon when bypassed. 2018-12-31 14:58:10 -08:00
Jared Boone
d0681933e6 PortaPack: Update TX gain label.
Turns out the HackRF code refers to MAX2837 TX VGA gain, which is mis-labeled as a baseband setting. It's actually in the IF portion of the TX path.
2018-12-31 14:47:42 -08:00
Jared Boone
bb059ddfa7 PortaPack: Store LNA state for use when radio path direction changes. 2018-12-31 14:22:49 -08:00
Jared Boone
fd65f35872 PortaPack: Draw gain value for LNA. 2018-12-31 14:22:22 -08:00
Jared Boone
9cce90b02e PortaPack: Define draw-dB function earier so it can be used for LNA. 2018-12-31 14:21:47 -08:00
Jared Boone
1775c44b79 PortaPack: Don't draw sample rate.
It looks ugly, needs fixing.
2018-12-31 14:21:08 -08:00
Jared Boone
c09f76a92c PortaPack: Consolidate color palette. 2018-12-31 14:07:39 -08:00
Jared Boone
53b1250061 PortaPack: Fix integer rendering so a 0 value doesn't show up as an empty string. 2018-12-31 10:59:40 -08:00
Jared Boone
de3f5a0e9f PortaPack: Add string draw fn, +dB draw fn. 2018-12-31 10:47:18 -08:00
Jared Boone
494f203f8d PortaPack: Clean up tuning frequency rendering, add spaces per 3-digit group for readability. 2018-12-31 10:36:17 -08:00
Jared Boone
f60b2479fb JTAG: Restore CPLD pin config functions, leave pins in pull-only state when not actively operating. 2018-12-31 10:12:28 -08:00
Jared Boone
2e6153a653 I2C: Device probe function I wrote, didn't need, but thought might be useful in the future. 2018-12-27 21:11:35 -08:00
Jared Boone
b35ec285b6 PortaPack UI: Miscellaneous clean-up
Remove "portapack" arg to many static functions, no idea why I thought that was necessary.
Add PortaPack presence detect function using JTAG.
Create a "hackrf_ui_t" type that has function pointers to a specific UI implementation, returned by a UI detection function.
2018-12-27 21:11:00 -08:00
Jared Boone
816d435dc5 Pin setup: Break out JTAG configuration, rework to consider PortaPack. 2018-12-27 20:33:33 -08:00
Jared Boone
bfd3b1b768 Set 1V8 enable state before configuring pin function or to output mode
...to avoid glitching 1V8 enable voltage.
2018-12-27 20:31:31 -08:00
Jared Boone
610e6b58cc Set VAA_ENABLE# state before setting GPIO to output.
...to avoid glitching the output voltage.
2018-12-27 20:29:25 -08:00
Jared Boone
5535cf059e Pin setup: Make GPIO direction reset the *first* step. 2018-12-27 20:26:55 -08:00
Jared Boone
0b46745aed OperaCake code conflicts with PortaPack code, make compile-time conditional. 2018-12-27 15:14:52 -08:00
Jared Boone
d8f579af2b Merge from mossmann/master 2018-12-27 14:56:29 -08:00
Jared Boone
88fb406a55 PortaPack: Conditionally claim JTAG pins in SCU #defines 2018-12-27 10:10:01 -08:00
Dominic Spill
82656b8f14 HackRF Opera Cake - GPIO test mode 2018-11-09 22:10:16 -07:00
Jared Boone
ccc86aad14 Add support for PortaPack user interface add-on board. 2018-08-01 21:05:10 -07:00
Michael Ossmann
991c5089a9 Merge branch 'glitch-fix' 2018-02-02 15:15:27 -07:00
Michael Ossmann
5d6667141e short pulses when enabling VAA to avoid a big voltage glitch 2018-01-28 16:24:48 -07:00
Michael Ossmann
b095c5326a eliminated minor glitch caused by enabling a GPIO output before setting its value 2018-01-28 16:16:35 -07:00
Dominic Spill
5f560d6ad3 Merge branch 'mossmann-master' into flash-investigation 2017-12-05 16:18:19 -07:00
Dominic Spill
3f569a8ad4 hackrf_clock: Allow CLKOUT to be enabled / disabled
hackrf_clock -o 1 / hackrf_clock -o 0
2017-11-07 11:23:48 -07:00
Dominic Spill
c416fa1294 SPI Flash: add function to clear SPI flash status register 2017-11-06 10:42:19 -07:00
Dominic Spill
8f544ee60d Add flash status read 2017-09-12 17:52:07 -06:00
schneider
1acd7ccf7c fix(rad1o): TX_RX_N is on GPIO1_11 2017-08-05 06:05:31 +02:00
schneider
4b0bb0ea55 refact(rad1o): Disable the CPU clock outputs in pin_setup() 2017-08-05 06:04:08 +02:00
schneider
03e472e458 fix(rad1o): Disable the VCO if the mixer is not in use 2017-08-05 06:01:53 +02:00
Dominic Spill
90d3f7f293 Remove unused ARRAY_SIZE definition 2017-07-11 18:27:24 -06:00
Dominic Spill
72a03cffa8 Merge pull request #382 from dominicgs/operaglasses
Opera glasses: allow user specified ranges for operacake ports
2017-06-02 10:23:24 -06:00
Dominic Spill
8c7941b0ef Opera glasses: allow user specified ranges for operacake ports
- HackRF switches antenna when tuning
 - ports specified using hackrf_operacake cmdline tool
 hackrf_operacake -f 2350:2800:0 -f 0:400:1 -f 400:700:2 -f 700:6000:3
2017-05-16 17:18:54 -06:00
Marco Bartolucci
a773b463cb cleanup 2017-05-16 15:37:27 +02:00
Marco Bartolucci
533f9ee332 Hardware (CPLD-based) synchronisation
=======================================

This commit allows to synchronise multiple HackRFs with a synchronisation error **below 1 sampling period**

> WARNING: Use this at your own risk. If you don't know what you are doing you may damage your HackRF.
> The author takes no responsability for potential damages

Usage example: synchronise two HackRFs
======================================
1. Chose the master HackRF which will send the synchronisation pulse (HackRF0). HackRF1 will represent the slave hackrf.
2. Retreive the serial number of both HackRFs using `hackrf_info`
3. Use a wire to connect `SYNC_CMD` of HackRF0 to `SYNC_IN` of HackRF0 and HackRF1
4. Run `hackrf_transfer` with the argument `-H 1` to enable hardware synchronisation:
    ```
    $ hackrf_tranfer ... -r rec1.bin -d HackRF1_serial -H 1 | hackrf_transfer ... -r rec0.bin -d HackRF0_serial -H 1
    ```
rec0.bin and rec1.bin will have a time offset below 1 sampling period.
The 1PPS output of GNSS receivers can be used to synchronise HackRFs even if they are far from each other.
>DON'T APPLY INCOMPATIBLE VOLTAGE LEVELS TO THE CPLD PINS

Signal | Header |Pin | Description
-------|--------|----|------------
`SYNC_IN` | P28 | 16 | Synchronisation pulse input
`SYNC_CMD` | P28 | 15 | Synchronisation pulse output

Note:
=====
I had to remove CPLD-based decimation to use a GPIO for enabling hardware.

More info:
==========
[M. Bartolucci, J. A. Del Peral-Rosado, R. Estatuet-Castillo, J. A. Garcia-Molina, M. Crisci and G. E. Corazza, "Synchronisation of low-cost open source SDRs for navigation applications," 2016 8th ESA Workshop on Satellite Navigation Technologies and European Workshop on GNSS Signals and Signal Processing (NAVITEC), Noordwijk, 2016, pp. 1-7.](http://ieeexplore.ieee.org/document/7849328/)

[Alternative link](http://spcomnav.uab.es/docs/conferences/Bartolucci_NAVITEC_2016.pdf)
2017-05-16 11:39:44 +02:00
Marco Bartolucci
747d8e2278 Removed decimation in CPLD 2017-05-15 12:56:51 +02:00
Dominic Spill
8b853266ef Power down CLK3 (CLKOUT) at boot, don't reset it when clocks are reset 2017-02-28 15:26:43 -07:00
Dominic Spill
00b6099bb3 Make comments more informative (possibly) 2017-02-28 15:25:27 -07:00
Dominic Spill
e7f890e0c2 Merge branch 'mossmann-master' into firmware_cleanup 2017-02-22 12:10:42 -07:00
Dominic Spill
0a48dccd66 CLOKOUT off by default 2017-02-21 18:38:50 -07:00
Dominic Spill
acaf0d192c Change RFFC5071 clock from 40MHz to 50MHz and invert it
Now the MAX2837 and RFFC5071 clocks are out of phase with each other
Hopefully this reduces some noise
2017-02-21 17:56:37 -07:00
Dominic Spill
15ea074bdb Clean up Si5351c initialisation code 2017-02-21 17:43:19 -07:00
Dominic Spill
3eb00ed0df Disable CLK7 and power down CLK6/7 to reduce emissions 2017-02-20 12:34:35 -07:00
schneider
d4c69890b5 fix(rad1o): Restore old clock behaviour for now. 2017-02-19 01:39:51 +01:00
Dominic Spill
ef695a36e0 Reinstate LPC4330 linker script 2017-02-17 07:49:16 -07:00