Previously CPLD programming involved a large 64kbyte buffer into which
the the entire bitstream would be completely downloaded, and at which
point the programming process would commence. This is needlessly
wasteful of memory. Moreover, it could lead to USB timeouts as the
firmware needs to wait the entire duration of the programming process
before returning an ACK to the host after the final SETUP data phase
packet.
Instead, we now receive 512 byte chunks of the bitstream and stream them
to the CPLD one at a time. We wait for each packet to be streamed out to
the CPLD before ACKing the packet to prevent active data being
overwritten.
pins b7 & b6 are floating, disable re-triggering
selecting a different HPC_STOP fixes the dc offset drift
disabling and enabling rx/tx after tuning triggers the dc offset
correction
