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25 Commits

Author SHA1 Message Date
Tobias Schneider
c05929fe25 fix(common, hackf_usb): Make it compile for rad10 2015-06-06 18:49:09 +02:00
Michael Ossmann
69c4997727 fixed bug #130, CLKIN failure 2014-08-28 11:34:30 -06:00
Michael Ossmann
15bda174c7 maintain PLLA on XTAL and PLLB on CLKIN at all times (makes automatic clock source switching more reliable) 2014-03-14 22:27:30 -06:00
Michael Ossmann
ca04d7c04b activated CLKOUT (always on) and CLKIN (automatically used when detected) 2014-03-14 21:28:13 -06:00
Jared Boone
fb5dc6d5e0 Merge remote-tracking branch 'mossmann/master' into jboone_refactor_20130906 
Conflicts:
	firmware/common/si5351c.c

Preferred Si5351C configuration that drives 40MHz into the LPC43xx GP_CLKIN.
Added HACKRF_ONE qualifier for CPLD TMS/TDI swap.
 2014-01-07 16:48:52 -08:00
Jared Boone
7f35ceaff2 Set Si5351C CLK7 output to drive LPC GP_CLKIN at 40MHz, so that activity (e.g. audio) on the LPC can be synchronized with the baseband sample rate. 2013-12-31 20:09:44 -08:00
Michael Ossmann
6b482b94da set crystal load capacitance to 8 pF 2013-12-12 15:47:00 -07:00
Michael Ossmann
99803c26cb another clock strength adjustment 2013-11-22 17:50:10 -07:00
Michael Ossmann
ebaccf46f4 adjusted clock generator output drive strength 2013-11-22 17:24:53 -07:00
Jared Boone
b285b91e4c Merge remote-tracking branch 'mossmann/master' into jboone_refactor_20130906 
Conflicts:
	firmware/common/hackrf_core.h
	firmware/common/rffc5071.c
 2013-11-20 18:43:40 -08:00
Michael Ossmann
5b14636c2c initial firmware support for HackRF One 2013-11-19 10:01:26 -07:00
Jared Boone
06da7fd83a Reduce drive strength from clock generator (Si5351C) to first mixer (RFFC5072). This reduces every-50MHz spurs in RX by 10 to 15dB. 2013-09-22 11:54:37 -07:00
Hoernchen
1e326997ed firmware: enable int mode if div is even integer 
to improve jitter performance
 2013-06-07 23:10:35 +02:00
Hoernchen
1925649a01 firmware: fractional sample rates 2013-06-07 14:29:14 +02:00
Hoernchen
a95f49b543 disable si clock to lpc 
leaving it on but unused causes major spurs to appear all over the
place..
 2013-06-05 17:35:01 +02:00
Hoernchen
7f6a730c6e si clock for the lpc 2013-05-29 17:12:06 +02:00
Jared Boone
4f9a5a1ba4 Fix-ups to copyrights -- missing e-mail address and inconsistent formatting. 2012-10-06 19:14:55 -07:00
Michael Ossmann
2c813ec41e Jawbreaker clock generator configuration 2012-09-19 13:43:16 -06:00
Michael Ossmann
cbd2d98c7d fixed bad output spectrum. problem was P3 = 0 in si5351c pll, similar to commit b595de647077f208c534e4efc0bce92f25378fb8 2012-08-22 10:41:53 -06:00
Jared Boone
9a53fd3a07 New CPLD .svf. 
Change Si5351C CLK2 to 10MHz.
Keep CLK3 at 20MHz, but not inverted.
Source SGPIO8 from P1_12 instead of P9_6. (See "SGPIO Clock Routing") modification at https://github.com/mossmann/hackrf/wiki/Future-Hardware-Modifications ).
 2012-06-15 16:12:35 -07:00
Michael Ossmann
ad080a355a pull request #10, resolved conflicts 2012-06-13 21:21:34 -06:00
Jared Boone
02f61f4d64 Added r_div argument to si5351c_configure_multisynth(). Modified Jellybean clock setup to provide 10MHz clock to MAX5864 and 20MHz to CPLD (both inverted and non-inverted). 2012-06-13 17:53:10 -07:00
Michael Ossmann
056ddd0601 r divider configurable, added CLK5 for mixer reference input 2012-06-13 16:02:40 -06:00
Michael Ossmann
aeced361cf migrated common stuff to libopencm3 2012-06-07 08:14:16 -06:00
Michael Ossmann
f01fc2d445 initial port of Jared\'s initialization code to libopencm3, not complete yet 2012-06-05 22:20:56 -06:00