Jared Boone
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bab6ec5fef
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Move buffer allocation to before enabling CPLD I/O, so as not to mess up I/Q synchronization.
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2012-06-15 16:16:05 -07:00 |
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Jared Boone
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e32a60495a
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Change initial TX output data to the neutral value (0x80).
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2012-06-15 16:14:58 -07:00 |
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Jared Boone
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59a5b92300
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Correct CPLD JTAG pin release code to properly tri-state the pins.
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2012-06-15 16:13:17 -07:00 |
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Jared Boone
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74ad447ec7
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More idiotic editor formatting fixup.
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2012-06-14 11:48:07 -07:00 |
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Jared Boone
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388cad86de
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Code to capture ADC data into a buffer using a tight loop on the M4.
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2012-06-14 11:31:11 -07:00 |
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Jared Boone
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878936645d
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Corrected my correction of my misunderstanding of how SGPIO_CTRL_ENABLE works. Turns out I *can* immediately disable a slice using ENABLE. If I want to synchronously disable a slice, I do it via DISABLE. And if I want to screw up my code, I (unwittingly) set all slices to synchronously disable, then configure SGPIO and watch my slices run once and stop. :-( All better now.
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2012-06-14 11:30:03 -07:00 |
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Jared Boone
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3c35e39e55
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Clean up SGPIO TX code a little bit.
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2012-06-13 22:00:37 -07:00 |
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Jared Boone
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b5ec859eaf
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Remove comment of dead code.
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2012-06-13 22:00:11 -07:00 |
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Jared Boone
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17446f6295
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Add RX test, which receives data into a single slice.
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2012-06-13 21:58:47 -07:00 |
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Jared Boone
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b7a46af009
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I was misusing SGPIO_CTRL_ENABLE. Instead, use SGPIO_CTRL_DISABLE to disable slices.
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2012-06-13 21:54:48 -07:00 |
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Jared Boone
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d6cf4ec014
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Initial SGPIO implementation. Sends a constant value to each channel of the DAC that can be measured as differential voltages to identify which channel is which.
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2012-06-13 18:04:13 -07:00 |
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