842 Commits

Author SHA1 Message Date
Jared Boone
b35ec285b6 PortaPack UI: Miscellaneous clean-up
Remove "portapack" arg to many static functions, no idea why I thought that was necessary.
Add PortaPack presence detect function using JTAG.
Create a "hackrf_ui_t" type that has function pointers to a specific UI implementation, returned by a UI detection function.
2018-12-27 21:11:00 -08:00
Jared Boone
816d435dc5 Pin setup: Break out JTAG configuration, rework to consider PortaPack. 2018-12-27 20:33:33 -08:00
Jared Boone
bfd3b1b768 Set 1V8 enable state before configuring pin function or to output mode
...to avoid glitching 1V8 enable voltage.
2018-12-27 20:31:31 -08:00
Jared Boone
610e6b58cc Set VAA_ENABLE# state before setting GPIO to output.
...to avoid glitching the output voltage.
2018-12-27 20:29:25 -08:00
Jared Boone
5535cf059e Pin setup: Make GPIO direction reset the *first* step. 2018-12-27 20:26:55 -08:00
Jared Boone
0b46745aed OperaCake code conflicts with PortaPack code, make compile-time conditional. 2018-12-27 15:14:52 -08:00
Jared Boone
d8f579af2b Merge from mossmann/master 2018-12-27 14:56:29 -08:00
Jared Boone
88fb406a55 PortaPack: Conditionally claim JTAG pins in SCU #defines 2018-12-27 10:10:01 -08:00
Dominic Spill
454e32b8c8 Travis artefacts (#564)
* Try artefacts deployed to gh_pages

* Try to use gh_pages from the travis_artefacts branch

* Try deploying to a different repo

* Try to organise files deployed to github pages

* Test pushing a local dir to master

* Try pushing to original repo

* Be verbose so I can debug it

* Setting env variables

* Oops, environment variables aren't what I thought

* Try to push to nightly repo

* Remove unused cp command

* Copy firmware to archive directory

* Fix pathing to artefacts

* Use TRAVIS_BUID_DIR instead of assuming path

* Use mkdir -p to ensure directories exist

* Put / back in to CPLD path

* Move repo to GSG

* Switch to master branch

* Add nightly deployment

* Fix escaping in sed command

* Allow firmware version styring to be overridden

* Fix some sed commands....

* Switch to master branch for builds
2018-12-20 20:38:10 -07:00
Dominic Spill
9da826e9ef Add Windows build art(e|i)facts (#561)
This includes:
 * Cmake clean up - thanks @Qyriad
 * Windows binaries saved after each appveyor build
 * A bump to the Visual Studio version that we use to build it
 * An appveyor cygwin script for building firmware, it doesn't work but it seems like someone might pick it up and make it work, or blow it away if we switch to Travis firmware artefacts
2018-12-05 18:45:26 -07:00
Dominic Spill
82656b8f14 HackRF Opera Cake - GPIO test mode 2018-11-09 22:10:16 -07:00
Jared Boone
ccc86aad14 Add support for PortaPack user interface add-on board. 2018-08-01 21:05:10 -07:00
Arnout Vandecappelle (Essensium/Mind)
a6284cb9ed Don't require a C++ compiler
By default, CMake assumes that the project is using both C and C++.  By
explicitly passing 'C' as argument of the project() macro, we tell CMake
that only C is used, which prevents CMake from erroring out if a C++
compiler doesn't exist.
2018-03-31 22:50:37 +02:00
Dominic Spill
bde5ca9f58 DFU serial number - avoid reading serial from flash chip
Set a DFU mode specific serial number
2018-03-27 18:08:49 -06:00
Dominic Spill
92f122d43a Firmware: no longer require dfu-prefix
it was adding a header that we weren't using anyway
2018-03-22 12:29:27 -06:00
Michael Ossmann
fc8fcd8616 added CPLD update requirement to firmware/README
improved cpld/README
fixes #458
2018-02-20 08:18:42 -07:00
Michael Ossmann
991c5089a9 Merge branch 'glitch-fix' 2018-02-02 15:15:27 -07:00
Michael Ossmann
5d6667141e short pulses when enabling VAA to avoid a big voltage glitch 2018-01-28 16:24:48 -07:00
Michael Ossmann
b095c5326a eliminated minor glitch caused by enabling a GPIO output before setting its value 2018-01-28 16:16:35 -07:00
Dominic Spill
5f560d6ad3 Merge branch 'mossmann-master' into flash-investigation 2017-12-05 16:18:19 -07:00
Dominic Spill
3f569a8ad4 hackrf_clock: Allow CLKOUT to be enabled / disabled
hackrf_clock -o 1 / hackrf_clock -o 0
2017-11-07 11:23:48 -07:00
Dominic Spill
c416fa1294 SPI Flash: add function to clear SPI flash status register 2017-11-06 10:42:19 -07:00
Dominic Spill
8f544ee60d Add flash status read 2017-09-12 17:52:07 -06:00
Dominic Spill
46945205f2 Add USB product string for rad1o badge 2017-08-10 16:12:40 +01:00
schneider
1acd7ccf7c fix(rad1o): TX_RX_N is on GPIO1_11 2017-08-05 06:05:31 +02:00
schneider
4b0bb0ea55 refact(rad1o): Disable the CPU clock outputs in pin_setup() 2017-08-05 06:04:08 +02:00
schneider
03e472e458 fix(rad1o): Disable the VCO if the mixer is not in use 2017-08-05 06:01:53 +02:00
Dominic Spill
90d3f7f293 Remove unused ARRAY_SIZE definition 2017-07-11 18:27:24 -06:00
Dominic Spill
72a03cffa8 Merge pull request #382 from dominicgs/operaglasses
Opera glasses: allow user specified ranges for operacake ports
2017-06-02 10:23:24 -06:00
Dominic Spill
8c7941b0ef Opera glasses: allow user specified ranges for operacake ports
- HackRF switches antenna when tuning
 - ports specified using hackrf_operacake cmdline tool
 hackrf_operacake -f 2350:2800:0 -f 0:400:1 -f 400:700:2 -f 700:6000:3
2017-05-16 17:18:54 -06:00
Marco Bartolucci
a773b463cb cleanup 2017-05-16 15:37:27 +02:00
Marco Bartolucci
533f9ee332 Hardware (CPLD-based) synchronisation
=======================================

This commit allows to synchronise multiple HackRFs with a synchronisation error **below 1 sampling period**

> WARNING: Use this at your own risk. If you don't know what you are doing you may damage your HackRF.
> The author takes no responsability for potential damages

Usage example: synchronise two HackRFs
======================================
1. Chose the master HackRF which will send the synchronisation pulse (HackRF0). HackRF1 will represent the slave hackrf.
2. Retreive the serial number of both HackRFs using `hackrf_info`
3. Use a wire to connect `SYNC_CMD` of HackRF0 to `SYNC_IN` of HackRF0 and HackRF1
4. Run `hackrf_transfer` with the argument `-H 1` to enable hardware synchronisation:
    ```
    $ hackrf_tranfer ... -r rec1.bin -d HackRF1_serial -H 1 | hackrf_transfer ... -r rec0.bin -d HackRF0_serial -H 1
    ```
rec0.bin and rec1.bin will have a time offset below 1 sampling period.
The 1PPS output of GNSS receivers can be used to synchronise HackRFs even if they are far from each other.
>DON'T APPLY INCOMPATIBLE VOLTAGE LEVELS TO THE CPLD PINS

Signal | Header |Pin | Description
-------|--------|----|------------
`SYNC_IN` | P28 | 16 | Synchronisation pulse input
`SYNC_CMD` | P28 | 15 | Synchronisation pulse output

Note:
=====
I had to remove CPLD-based decimation to use a GPIO for enabling hardware.

More info:
==========
[M. Bartolucci, J. A. Del Peral-Rosado, R. Estatuet-Castillo, J. A. Garcia-Molina, M. Crisci and G. E. Corazza, "Synchronisation of low-cost open source SDRs for navigation applications," 2016 8th ESA Workshop on Satellite Navigation Technologies and European Workshop on GNSS Signals and Signal Processing (NAVITEC), Noordwijk, 2016, pp. 1-7.](http://ieeexplore.ieee.org/document/7849328/)

[Alternative link](http://spcomnav.uab.es/docs/conferences/Bartolucci_NAVITEC_2016.pdf)
2017-05-16 11:39:44 +02:00
Marco Bartolucci
747d8e2278 Removed decimation in CPLD 2017-05-15 12:56:51 +02:00
Marco Bartolucci
d47dece3ba Fixed indentation 2017-05-15 11:49:23 +02:00
Marco Bartolucci
808fd9410e Bump to latest version
Merge remote-tracking branch 'upstream/master'
2017-05-05 11:58:43 +02:00
Dominic Spill
8b853266ef Power down CLK3 (CLKOUT) at boot, don't reset it when clocks are reset 2017-02-28 15:26:43 -07:00
Dominic Spill
00b6099bb3 Make comments more informative (possibly) 2017-02-28 15:25:27 -07:00
Dominic Spill
e7f890e0c2 Merge branch 'mossmann-master' into firmware_cleanup 2017-02-22 12:10:42 -07:00
Dominic Spill
0a48dccd66 CLOKOUT off by default 2017-02-21 18:38:50 -07:00
Dominic Spill
acaf0d192c Change RFFC5071 clock from 40MHz to 50MHz and invert it
Now the MAX2837 and RFFC5071 clocks are out of phase with each other
Hopefully this reduces some noise
2017-02-21 17:56:37 -07:00
Dominic Spill
15ea074bdb Clean up Si5351c initialisation code 2017-02-21 17:43:19 -07:00
Dominic Spill
3eb00ed0df Disable CLK7 and power down CLK6/7 to reduce emissions 2017-02-20 12:34:35 -07:00
schneider
d4c69890b5 fix(rad1o): Restore old clock behaviour for now. 2017-02-19 01:39:51 +01:00
Dominic Spill
ef695a36e0 Reinstate LPC4330 linker script 2017-02-17 07:49:16 -07:00
Marco Bartolucci
9d6f2a7e9c Fixed sgpio_if readme 2017-02-17 14:05:33 +01:00
Marco Bartolucci
fa6bde951c Added CPLD-based synchronization
This is a proof of concept and it's still very crude
For more info read (http://spcomnav.uab.es/docs/conferences/Bartolucci_NAVITEC_2016.pdf)
2017-02-17 13:58:55 +01:00
Dominic Spill
a4036eab76 Remove last mentions of Jellybean 2017-02-16 18:03:32 -07:00
Michael Ossmann
79f95abdb3 correct discrepancy between number of samples and number of bytes in blocks of samples
related to #346
2017-02-16 12:46:17 -07:00
Dominic Spill
09eb15cb53 Remove unused development firmware from build 2017-02-14 21:34:44 -07:00
Dominic Spill
9e3b69a9b7 Remove source for development firmwares 2017-02-14 21:34:28 -07:00