Sojus07/hackrf
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3 Commits

Author SHA1 Message Date
Jared Boone
9a53fd3a07 New CPLD .svf. 
Change Si5351C CLK2 to 10MHz.
Keep CLK3 at 20MHz, but not inverted.
Source SGPIO8 from P1_12 instead of P9_6. (See "SGPIO Clock Routing") modification at https://github.com/mossmann/hackrf/wiki/Future-Hardware-Modifications ).
 2012-06-15 16:12:35 -07:00
Jared Boone
9c50b7de26 Updated SVF from committed project files. 2012-06-09 22:34:32 -07:00
Jared Boone
07b6f81a6c Initial implementation of MAX5864 <-> SGPIO interface via Xilinx CoolRunner-II CPLD. 2012-06-09 22:02:45 -07:00