Sojus07/hackrf
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343 Commits

Author SHA1 Message Date
Michael Ossmann
7de081c7d5 Bubblegum redesign assuming TX_BALUN and RX_BALUN can operate from 10 MHz to 6 GHz 2012-06-21 00:15:04 -06:00
Michael Ossmann
0a5fed5933 tied unused logic input to VCC 2012-06-20 15:14:42 -06:00
Michael Ossmann
0277159ce5 tied unused logic input to VCC 2012-06-20 13:56:51 -06:00
Jared Boone
2e16f51252 Python program to verify logic on the Lollipop board. 2012-06-19 23:09:42 -07:00
Michael Ossmann
2f5b4fb778 updated layout for switch logic bug fix 2012-06-20 00:08:12 -06:00
Michael Ossmann
2a9502cb50 fixed more switch logic bugs 2012-06-19 23:51:57 -06:00
Michael Ossmann
81f840e623 finished first pass at schematic for bubblegum, an alternative wideband front end 2012-06-19 17:05:41 -06:00
Michael Ossmann
3d7d80c14a reworked layout to fix switch logic bugs 2012-06-19 12:23:53 -06:00
Michael Ossmann
c7aeb2007f fixed PVQFN-14 modules for logic ICs (pins were numbered incorrectly) 2012-06-19 10:48:42 -06:00
Michael Ossmann
53389064f1 fixed switch logic errors in schematic 2012-06-18 21:35:13 -06:00
Jared Boone
9a53fd3a07 New CPLD .svf. 
Change Si5351C CLK2 to 10MHz.
Keep CLK3 at 20MHz, but not inverted.
Source SGPIO8 from P1_12 instead of P9_6. (See "SGPIO Clock Routing") modification at https://github.com/mossmann/hackrf/wiki/Future-Hardware-Modifications ).
 2012-06-15 16:12:35 -07:00
Jared Boone
d68036f79d Eliminate ill-conceived HOST_CLK from CPLD. 
Rearrange clocks to not use AC-coupled CLK1 from Si5351C.
Move CODEC_CLK to GCLK1, CODEC_X2_CLK (now HOST_CLK, too) to GCLK2.
Add trace on Jellybean PCB to connect GCLK2 to LPC4330 pin 56 (P1_12) -- a different SGPIO8.
 2012-06-14 19:08:20 -07:00
Michael Ossmann
e71163b44a noting discrepancy between implementations 2012-06-13 21:27:14 -06:00
Jared Boone
9c50b7de26 Updated SVF from committed project files. 2012-06-09 22:34:32 -07:00
Jared Boone
89314d40d6 Added Bus Blaster programming script. Added README explaining project contents and programming process. 2012-06-09 22:34:01 -07:00
Jared Boone
07b6f81a6c Initial implementation of MAX5864 <-> SGPIO interface via Xilinx CoolRunner-II CPLD. 2012-06-09 22:02:45 -07:00
Michael Ossmann
9c154c5e3e completed BOM info 2012-06-04 14:44:25 -06:00
Michael Ossmann
1958592bb4 connected some too-close ground areas to each other 2012-06-04 09:57:19 -06:00
Michael Ossmann
ad00162a34 mask and paste clearances 2012-06-04 09:51:20 -06:00
Michael Ossmann
8de59607f8 plot options 2012-06-03 20:56:59 -06:00
Michael Ossmann
0baf5ad41a fixed some minor DRC errors 2012-06-03 20:51:56 -06:00
Michael Ossmann
b84b6e7a55 stitched ground planes 2012-06-03 20:44:31 -06:00
Michael Ossmann
50dbd0367e filled in back QFN thermal relief 2012-06-03 20:16:40 -06:00
Michael Ossmann
3e0a2050db updated SMA module to match CONREVSMA003.062 recommended footprint 2012-06-03 20:13:02 -06:00
Michael Ossmann
ce998e3750 made some power supply tracks and vias bigger 2012-06-03 18:01:05 -06:00
Michael Ossmann
ebf51131ae removed front zone 2012-06-02 15:37:55 -06:00
Michael Ossmann
b36de1ea8b fixed some missing vias 2012-06-02 09:32:22 -06:00
Michael Ossmann
4f9cf4ae00 finished rearranging RF section 2012-06-02 00:15:22 -06:00
Michael Ossmann
9d035488a3 more layout updates 2012-06-01 16:51:53 -06:00
Michael Ossmann
3f5f7ac49f started moving things around 2012-06-01 13:40:25 -06:00
Michael Ossmann
14e7d06182 corrected T3 and T6 orientation in schematic 2012-06-01 13:28:00 -06:00
Michael Ossmann
bda6bf5832 destroyed my layout by reading in recent changes from schematic. here we go! 2012-06-01 13:19:42 -06:00
Michael Ossmann
3522eb6723 swapped RX highpass and lowpass paths so that TX highpass and RX highpass are not adjacent. 2012-06-01 13:15:25 -06:00
Michael Ossmann
2e905170f8 Merge branch 'master' of github.com:mossmann/hackrf 2012-05-30 15:21:06 -06:00
Michael Ossmann
acc21d011f grounded U17 and U19 center pads 2012-05-30 15:20:46 -06:00
TitanMKD
4569ac35a4 Merge branch 'master' of git://github.com/mossmann/hackrf 2012-05-30 07:08:12 +02:00
Michael Ossmann
3977c7ab0e selected 0603 footprint for L1 and L2, moved L3 and made DNP 2012-05-29 17:17:15 -06:00
Michael Ossmann
9e6427ecf2 changed to RFXF9503 balun on lowpass paths 2012-05-29 17:12:29 -06:00
TitanMKD
ba1880799a JellyBean TSP62410 computation theory for output voltage. 2012-05-29 23:11:14 +02:00
TitanMKD
a27210c034 Added JellyBean Pin to be used with NXP http://www.lpcware.com/content/nxpfile/lpc43xx-pin-mux-tool 2012-05-29 23:08:50 +02:00
TitanMKD
ba14f7e539 Fix jellybean_BOM.ods with 3.3V fix. 2012-05-29 23:05:28 +02:00
TitanMKD
71879fc05f JellyBean BOM with DigiKey Part Number 2012-05-28 11:41:41 +02:00
Michael Ossmann
27483cb044 silkscreen 2012-05-20 21:48:49 -06:00
Michael Ossmann
26155653f0 front and back zones 2012-05-20 21:44:43 -06:00
Michael Ossmann
2573bb63d6 single-ended traces 2012-05-20 18:50:23 -06:00
Michael Ossmann
a6f91b89c0 adjusted switch control signals 2012-05-20 16:52:41 -06:00
Michael Ossmann
2d692bd7d9 finished switch control signals, though some will have to be redone 2012-05-20 11:21:34 -06:00
Michael Ossmann
1c6ce610ec started switch control layout 2012-05-19 23:19:50 -06:00
Michael Ossmann
d22d6e92e1 fixed QFN14 module 2012-05-19 22:43:50 -06:00
Michael Ossmann
ec73993459 still more layout, selected part for L1 and L2, will need to change to 0603 2012-05-19 18:08:31 -06:00