Sojus07/hackrf
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320 Commits

Author SHA1 Message Date
Jared Boone
6c0d803647 Cleaned up management of SGPIO and transceiver mode state vs. USB configuration state. This should help with power management. It may also be necessary when operating at low speed (48MHz), to keep the SGPIO interrupts from chewing up ALL available CPU cycles. 2013-09-04 16:27:43 -07:00
Jared Boone
1f5b979fd9 Added usb_set_configuration_changed_cb() call that bgamari fixed in his as-yet-unmerged USB branch. 2013-09-04 16:24:19 -07:00
Jared Boone
d76d72665e Adjusted cpu_clock_pll1_low_speed() to operate at 48MHz, as per several comments with the code. The actual MSEL value was previously selecting 84MHz. 2013-09-04 16:23:32 -07:00
Jared Boone
237bf6ecdb Pulled redundant PLL1 initialization code from cpu_clock_init(). Called cpu_clock_pll1_low_speed() instead. 2013-09-04 16:22:41 -07:00
Jared Boone
189d245868 Merge remote-tracking branch 'TitanMKD/master' into titanmkd_overclock_fix 
Conflicts:
	firmware/hackrf_usb/hackrf_usb.c
 2013-09-04 12:41:03 -07:00
Jared Boone
a90c3b2324 Merge pull request #100 from jboone/master 
Incorporate bgamari changes for libopencm3 upstream.
 2013-09-02 11:10:11 -07:00
TitanMKD
24ed48d93a Fix for "issues/62 fix PLL1 overclock bug" see hackrf_core.c -> cpu_clock_init() 
Fix for "issues/78 startup current too high" see hackrf_core.c -> New functions cpu_clock_pll1_low_speed()/cpu_clock_pll1_max_speed() & hackrf_usb.c to switch low_speed/max_speed.
 2013-08-28 22:01:57 +02:00
Michael Ossmann
2648107a0b added dfu-util requirement 2013-08-11 14:56:32 -06:00
Ben Gamari
4822512dac Bump libopencm3 2013-07-07 18:51:50 -04:00
Ben Gamari
2717b7534e firmware/: Update #includes for libopencm3 merge 2013-07-07 17:48:54 -04:00
Ben Gamari
3dbe817b09 firmware/: Use uint32_t instead of u32 2013-07-07 17:48:54 -04:00
Ben Gamari
1bbe375746 A few more changes due to the libopencm3 merge 2013-07-07 17:48:54 -04:00
Ben Gamari
98f30188c1 Ensure that LPC43XX is defined for libopencm3 2013-07-07 17:48:54 -04:00
Ben Gamari
ddd7d8ca71 Fix NVIC interrupt macro names 
In libopencm3 master the NVIC macros are prefixed with NVIC_ not
NVIC_M4_
 2013-07-07 17:48:54 -04:00
Ben Gamari
fac5d0dfba Bump libopencm3 2013-07-07 17:48:54 -04:00
Ben Gamari
0972829ce5 usb: Rework configuration change notification 2013-07-01 00:25:22 -04:00
Ben Gamari
8a529617e5 Build against libopencm3 submodule tree by default 2013-07-01 00:21:49 -04:00
Ben Gamari
21a83179d8 Add libopencm3 submodule 2013-07-01 00:21:27 -04:00
Hoernchen
b33f534da0 firmware, lib: update comments, doc 2013-06-17 12:32:12 +02:00
Hoernchen
839a1a170f fw: dc offset correction fix 
pins b7 & b6 are floating, disable re-triggering
selecting a different HPC_STOP fixes the dc offset drift
disabling and enabling rx/tx after tuning triggers the dc offset
correction
 2013-06-16 20:26:02 +02:00
Hoernchen
3f6c91a5db firmware: automagically update freq when changing the if freq 2013-06-16 20:25:36 +02:00
Hoernchen
8063bd8207 firmware: if precision 2013-06-16 20:24:32 +02:00
Hoernchen
a6696de1d2 fw: ack 2013-06-16 20:24:19 +02:00
Hoernchen
bee537dc01 firmware: rffc frac, if gain 2013-06-16 20:23:47 +02:00
Hoernchen
8f55436cd1 firmware: fix a warning 2013-06-09 09:15:35 -06:00
Hoernchen
deafbab9fc lib: make sure to tell the linker that we're hardfloat, or it will choose the wrong libgcc.a... 2013-06-09 00:10:05 +02:00
Hoernchen
fe7558fcf3 lib/fw: rename the sample rate function 2013-06-09 00:09:46 +02:00
Sylvain Munaut
f0c7fe66f1 firmware: New fractional sample rate algorithm and usb command 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2013-06-09 00:08:18 +02:00
Hoernchen
1e326997ed firmware: enable int mode if div is even integer 
to improve jitter performance
 2013-06-07 23:10:35 +02:00
Hoernchen
1925649a01 firmware: fractional sample rates 2013-06-07 14:29:14 +02:00
Sylvain Munaut
472bcd414a firmware/build: Use gnu99 coding convention 
C99 doesn't require/support anonymous struct/unions in some GCC versions
and those are used a lot.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2013-06-06 22:52:40 +02:00
Hoernchen
a95f49b543 disable si clock to lpc 
leaving it on but unused causes major spurs to appear all over the
place..
 2013-06-05 17:35:01 +02:00
Hoernchen
b6a0b09b1d firmware: remove 5mhz option 2013-05-29 17:47:02 +02:00
Hoernchen
7f6a730c6e si clock for the lpc 2013-05-29 17:12:06 +02:00
Hoernchen
233c56c79d libhackrf/firmware: merge txvga gain into one gain range of 0-47 2013-05-29 00:53:41 +02:00
Hoernchen
19e8628650 firmware: fix plus 16db tx gain 2013-05-27 15:28:51 +02:00
Hoernchen
abc3cd1f4f firmware: gain control 2013-05-27 14:01:22 +02:00
Michael Ossmann
9276b9e89a moved cpld stuff out of hardware/jellybean where people would be unlikely to look for it 2013-05-18 09:48:37 -06:00
Michael Ossmann
389cbc6ac4 renamed usb_performance to hackrf_usb 2013-05-18 08:51:34 -06:00
TitanMKD
18932692ab Updated hackrf_transfer(host) and ubs_performance(firmware) extended frequency range from 5MHz to 6800MHz. 2013-05-17 23:41:32 +02:00
Michael Ossmann
60d21a3310 commenting out CGU_PLL1_CTRL_DIRECT=1 because it breaks boot from spifi 2013-05-11 18:55:00 -06:00
Jared Boone
d0e609429d Merge branch 'master' of https://github.com/mossmann/hackrf 2013-05-11 16:59:00 -07:00
Jared Boone
1723cd12a1 Oops, read PLL1 documentation again. Looks like FBSEL=1 is for "normal operation". So include that, but use DIRECT=1 to skip the PSEL divider (which would prevent us producing 204MHz from an in-spec PLL frequency). 2013-05-11 12:25:54 -07:00
Jared Boone
e065cdfe20 Slowed down edges on LED and power enable signals -- they don't need to be fast, and this *might* have a negligible but positive effect on noise. 2013-05-11 12:13:00 -07:00
Jared Boone
d9884af8b8 PLL1 was misconfigured to run at 408MHz (way out of spec) instead of 204MHz. Corrected this by using DIRECT=1 instead of FBSEL=1. 2013-05-11 12:11:37 -07:00
Jared Boone
a4a2a3d6ba Added SCU pinmux data for USB LEDs, configured USB LEDs to be outputs (not float). 2013-05-11 08:09:07 -07:00
TitanMKD
418680aed2 Fixed libhackrf, hackrf_cpldjtag (host) & usb_performance (firmware) to update CPLD through USB. 
Use latest CPLD bitstream with following command line:
hackrf_cpldjtag.exe -x hackrf\hardware\jellybean\sgpio_if\default.xsvf
 2013-05-09 00:29:42 +02:00
TitanMKD
8777f93721 Cleanup on xxx_rom_to_ram directory now it contains only makefile, removed redundant .c file from xxx dir. 
Fixed IAP "IAP_CMD_READ_SERIAL_NO" for LPC43xx flashless part not supporting IAP by using SPIFI w25q80bv Unique ID(64bits).
Fixed SPIFI erase/program also now it with check SPIFI w25q80bv Device ID = 0x13 at start of w25q80bv_setup()/w25q80bv_chip_erase()/w25q80bv_program().
 2013-04-07 18:55:12 +02:00
TitanMKD
b8590db02a Comment fix. 2013-04-04 19:48:28 +02:00
TitanMKD
294e958472 sgpio_if (top.vhd) CPLD VHDL fix for IQ/aliasing problems for ADC. (cpldjtagprog => sgpio_if_xsvf.h updated to rebuild). 
usb_performance.c SGPIO IQ fix for ADC (QI->IQ) for new CPLD (use usb_performance_rom_to_ram version else there is some packet lost even at 10Mhz sampling rate => make -f Makefile_rom_to_ram.)
 2013-04-04 19:43:30 +02:00