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222 Commits

Author SHA1 Message Date
Michael Ossmann
66fd66274f rough positions 2012-07-11 17:37:18 -06:00
Michael Ossmann
ad18781463 finished modules and selection 2012-07-11 13:26:00 -06:00
Michael Ossmann
ec807b943f started module selection, Anaren balun module 2012-07-08 14:53:25 -06:00
Michael Ossmann
b137550c60 reoriented filters 2012-07-06 14:57:40 -06:00
Michael Ossmann
a77682f04f switched to 0.05 pF TVS diodes 2012-07-06 14:26:47 -06:00
Michael Ossmann
2516504fca ferrite beads per TRF3765 recommendations 2012-07-06 13:20:03 -06:00
Michael Ossmann
7c9c840ad7 optional LO filters 2012-07-06 12:45:19 -06:00
Michael Ossmann
c0538167ba reworked balun bias again 2012-07-05 18:23:33 -06:00
Michael Ossmann
22fe7ee23d fixed balun bias 2012-07-05 18:00:15 -06:00
Michael Ossmann
5174f0632f updated Anaren balun topology 2012-07-05 17:47:45 -06:00
Michael Ossmann
130a15df37 renamed switch signals - hopefully clearer 2012-07-01 15:21:49 -06:00
Michael Ossmann
c641f36136 reference clock divider 2012-07-01 14:26:47 -06:00
Michael Ossmann
a02ce32809 fixed LO bypass mode by introducing intermediate mixer bias voltage 2012-07-01 14:00:27 -06:00
Michael Ossmann
44fb10d0ab noticed bias problem with LO bypass mode 2012-07-01 07:31:27 -06:00
Michael Ossmann
ac76517a1c loop filter values for PFD at 1.6 MHz 2012-06-30 12:23:21 -06:00
Michael Ossmann
7cd104dc95 passive values 2012-06-27 22:46:06 -06:00
Michael Ossmann
0909f42404 bom info 2012-06-27 22:18:50 -06:00
Michael Ossmann
7ac90cd308 matched n-channel mosfets to keep impedance the same between differential paths 2012-06-27 21:57:07 -06:00
Michael Ossmann
2c43a1d5ed fixed p-channel mosfet orientation 2012-06-27 21:52:24 -06:00
Michael Ossmann
ad5a106f68 Merge branch 'master' of github.com:mossmann/hackrf 2012-06-25 23:33:34 -06:00
Michael Ossmann
c5071f40f2 name and date on silkscreen 2012-06-23 08:22:28 -06:00
TitanMKD
1df6c29fa7 Merge branch 'master' of git://github.com/mossmann/hackrf 2012-06-22 18:13:53 +02:00
Michael Ossmann
9535249efc forgot to redo zones 2012-06-21 19:11:56 -06:00
Michael Ossmann
10133bdf27 redid highpass filter module now that I understand the drawing in the datasheet 2012-06-21 19:10:58 -06:00
Michael Ossmann
e232f7df20 flipped U8 to make more sense in the schematic 2012-06-21 18:56:16 -06:00
Michael Ossmann
c9444582b2 fixed LP0603 pinout, footprint 2012-06-21 18:48:31 -06:00
TitanMKD
bae1cc7c63 Merge branch 'master' of git://github.com/jboone/hackrf 2012-06-21 22:37:54 +02:00
Michael Ossmann
5207489527 disconnected pin 5 per B0310J50100AHF datasheet 2012-06-21 12:06:40 -06:00
Michael Ossmann
69935ee88c minor cleanup 2012-06-21 11:46:46 -06:00
Michael Ossmann
7de081c7d5 Bubblegum redesign assuming TX_BALUN and RX_BALUN can operate from 10 MHz to 6 GHz 2012-06-21 00:15:04 -06:00
Michael Ossmann
0a5fed5933 tied unused logic input to VCC 2012-06-20 15:14:42 -06:00
Michael Ossmann
0277159ce5 tied unused logic input to VCC 2012-06-20 13:56:51 -06:00
Jared Boone
2e16f51252 Python program to verify logic on the Lollipop board. 2012-06-19 23:09:42 -07:00
Michael Ossmann
2f5b4fb778 updated layout for switch logic bug fix 2012-06-20 00:08:12 -06:00
Michael Ossmann
2a9502cb50 fixed more switch logic bugs 2012-06-19 23:51:57 -06:00
Michael Ossmann
81f840e623 finished first pass at schematic for bubblegum, an alternative wideband front end 2012-06-19 17:05:41 -06:00
Michael Ossmann
3d7d80c14a reworked layout to fix switch logic bugs 2012-06-19 12:23:53 -06:00
Michael Ossmann
c7aeb2007f fixed PVQFN-14 modules for logic ICs (pins were numbered incorrectly) 2012-06-19 10:48:42 -06:00
Michael Ossmann
53389064f1 fixed switch logic errors in schematic 2012-06-18 21:35:13 -06:00
Jared Boone
9a53fd3a07 New CPLD .svf. 
Change Si5351C CLK2 to 10MHz.
Keep CLK3 at 20MHz, but not inverted.
Source SGPIO8 from P1_12 instead of P9_6. (See "SGPIO Clock Routing") modification at https://github.com/mossmann/hackrf/wiki/Future-Hardware-Modifications ).
 2012-06-15 16:12:35 -07:00
Jared Boone
d68036f79d Eliminate ill-conceived HOST_CLK from CPLD. 
Rearrange clocks to not use AC-coupled CLK1 from Si5351C.
Move CODEC_CLK to GCLK1, CODEC_X2_CLK (now HOST_CLK, too) to GCLK2.
Add trace on Jellybean PCB to connect GCLK2 to LPC4330 pin 56 (P1_12) -- a different SGPIO8.
 2012-06-14 19:08:20 -07:00
Michael Ossmann
e71163b44a noting discrepancy between implementations 2012-06-13 21:27:14 -06:00
Jared Boone
9c50b7de26 Updated SVF from committed project files. 2012-06-09 22:34:32 -07:00
Jared Boone
89314d40d6 Added Bus Blaster programming script. Added README explaining project contents and programming process. 2012-06-09 22:34:01 -07:00
Jared Boone
07b6f81a6c Initial implementation of MAX5864 <-> SGPIO interface via Xilinx CoolRunner-II CPLD. 2012-06-09 22:02:45 -07:00
Michael Ossmann
9c154c5e3e completed BOM info 2012-06-04 14:44:25 -06:00
Michael Ossmann
1958592bb4 connected some too-close ground areas to each other 2012-06-04 09:57:19 -06:00
Michael Ossmann
ad00162a34 mask and paste clearances 2012-06-04 09:51:20 -06:00
Michael Ossmann
8de59607f8 plot options 2012-06-03 20:56:59 -06:00
Michael Ossmann
0baf5ad41a fixed some minor DRC errors 2012-06-03 20:51:56 -06:00