Jared Boone
63b1a25979
Consolidate a few clock setup tasks that repeat among many projects into cpu_clock_init().
2012-10-17 11:45:30 -07:00
Jared Boone
685f5cdd6e
More detail in comments about Jellybean/Lemondrop clock destinations.
2012-10-10 11:51:06 -07:00
Jared Boone
4f9a5a1ba4
Fix-ups to copyrights -- missing e-mail address and inconsistent formatting.
2012-10-06 19:14:55 -07:00
Jared Boone
a975fbc577
Replaced apparently incorrect PLL0USB MDIV and NP_DIV values with values straight out of the User Manual's table 94.
2012-09-27 19:29:43 -07:00
Jared Boone
aaaf14819a
Move PLL1/M4 CLK up to full speed (204MHz) in two steps, according to UM chapter 11.2.1.
2012-09-27 18:58:00 -07:00
Jared Boone
776c502628
More tweaks related to CGU #define changes.
2012-09-27 17:55:54 -07:00
Jared Boone
416cdc6b20
Added missing hackrf_core pin_setup() and enable_1v8_power(), which have somehow gone missing.
2012-09-27 16:26:47 -07:00
Michael Ossmann
425a384832
Jawbreaker LPC crystal oscillator startup
2012-09-20 10:53:07 -06:00
Michael Ossmann
2c813ec41e
Jawbreaker clock generator configuration
2012-09-19 13:43:16 -06:00
Michael Ossmann
7d0c572569
Jawbreaker mixer serial interface support
2012-09-19 11:55:24 -06:00
Michael Ossmann
344a2f2a83
more clock generator config fixes
2012-08-23 12:59:49 -06:00
Jared Boone
9a53fd3a07
New CPLD .svf.
...
Change Si5351C CLK2 to 10MHz.
Keep CLK3 at 20MHz, but not inverted.
Source SGPIO8 from P1_12 instead of P9_6. (See "SGPIO Clock Routing") modification at https://github.com/mossmann/hackrf/wiki/Future-Hardware-Modifications ).
2012-06-15 16:12:35 -07:00
Jared Boone
f08fc3bb51
Pulled SSP1 configuration for MAX2837 into hackrf_core. Added SSP1 configuration for MAX5864. Added #defines for manipulating CS of both MAX parts. Changed a couple of #define names to be consistent with other names. Added explicit manipulation of MAX2837 CS via GPIO.
2012-06-14 13:06:10 -07:00
Michael Ossmann
ad080a355a
pull request #10 , resolved conflicts
2012-06-13 21:21:34 -06:00
Jared Boone
61b7b76912
OOPS. Missed changes from clock reconfiguration two commits (and five minutes) ago.
2012-06-13 17:58:14 -07:00
Michael Ossmann
056ddd0601
r divider configurable, added CLK5 for mixer reference input
2012-06-13 16:02:40 -06:00
TitanMKD
352b82f641
Fixed Clock Init (to be tested on other board).
2012-06-08 02:24:05 +02:00
Michael Ossmann
9a7219eb4d
removed PLL1 stages as they no longer seem to be necessary since the power-down fix
2012-06-07 13:40:59 -06:00
Michael Ossmann
98b6e92f97
fixed PLL1 startup problem by not powering it down first
2012-06-07 13:28:47 -06:00
Michael Ossmann
d1d1434fed
bring up PLL1 in stages
2012-06-07 12:00:30 -06:00
Michael Ossmann
aeced361cf
migrated common stuff to libopencm3
2012-06-07 08:14:16 -06:00
TitanMKD
acc806d5ce
* Add PIN_EN1V8 (1V8 work fine 1V8 LED is set to ON), and PIN_BOOT0, 1, 2 & 3(read only).
...
* Fixed wait() by using volatile else the loop was removed by GCC.
Tested it with SPIFI work fine:
SPIFI tested with LPCXpresso+NXP LPC Link (from LPCXpresso Board LPC1769 Debugger)
-> Program Flash with Flash Driver LPC1850A_4350A_SPIFI.cfx
-> Select file: firmware\blinky\blinky.bin
-> Base address 0x14000000 & option Erase only required pages
2012-05-28 00:02:48 +02:00
Michael Ossmann
a748e31328
started firmware directory with some basic stuff
2012-05-21 11:33:46 -06:00
