Jared Boone
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9a53fd3a07
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New CPLD .svf.
Change Si5351C CLK2 to 10MHz.
Keep CLK3 at 20MHz, but not inverted.
Source SGPIO8 from P1_12 instead of P9_6. (See "SGPIO Clock Routing") modification at https://github.com/mossmann/hackrf/wiki/Future-Hardware-Modifications ).
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2012-06-15 16:12:35 -07:00 |
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Michael Ossmann
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ad080a355a
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pull request #10, resolved conflicts
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2012-06-13 21:21:34 -06:00 |
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Jared Boone
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02f61f4d64
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Added r_div argument to si5351c_configure_multisynth(). Modified Jellybean clock setup to provide 10MHz clock to MAX5864 and 20MHz to CPLD (both inverted and non-inverted).
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2012-06-13 17:53:10 -07:00 |
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Michael Ossmann
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056ddd0601
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r divider configurable, added CLK5 for mixer reference input
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2012-06-13 16:02:40 -06:00 |
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Michael Ossmann
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aeced361cf
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migrated common stuff to libopencm3
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2012-06-07 08:14:16 -06:00 |
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Michael Ossmann
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f01fc2d445
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initial port of Jared\'s initialization code to libopencm3, not complete yet
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2012-06-05 22:20:56 -06:00 |
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