Jared Boone
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02ba23bf68
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Fix broken sgpio-rx project, broken due to massive changes to how RF path and tuning is done.
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2013-11-20 15:24:50 -08:00 |
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Jared Boone
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893c20e41f
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Fix naming problem with SGPIO test project. This is due to my use of VPATH in Makefile_inc.mk, which I'm starting to regret a little bit...
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2013-11-20 15:24:14 -08:00 |
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Jared Boone
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552dbe4a6d
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Add sgpio.c to C files, now required for pin initialization.
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2013-11-20 15:23:26 -08:00 |
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Jared Boone
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6a03f157ff
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With Makefile RAM/SPIFI option, remove/rework redundant "rom_to_ram" projects.
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2013-11-20 15:21:40 -08:00 |
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Jared Boone
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c365d0a37e
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Add memory regions for M0 code to live. In the "rom_to_ram" (SPIFI) version, put M0 binary in ROM. In the RAM version, put M0 code in the destination RAM region.
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2013-11-20 15:14:13 -08:00 |
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Jared Boone
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31a55d0e9b
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Assembly file that includes M0 binary into a .o to be linked into the M4 binary. There's certainly a more elegant way, but for now...
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2013-11-20 15:13:18 -08:00 |
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Jared Boone
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e29ec6b084
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Add default M0 code that just loops forever, if a project doesn't specify any SRC_M0_[CS] files.
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2013-11-20 15:11:54 -08:00 |
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Jared Boone
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91a7ca4983
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Fix return value on SGPIO decimation function.
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2013-11-20 15:08:59 -08:00 |
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Jared Boone
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e3f9e204c1
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Relocate SGPIO pin configuration -- it only needs to be done once.
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2013-11-20 13:22:19 -08:00 |
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Jared Boone
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39276f162c
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Add M0 linker script.
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2013-11-19 19:52:50 -08:00 |
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Jared Boone
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3bf6573dc6
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Add skip-every-N function to CPLD, where N is controlled by three input pins from the microcontroller.
Updated SGPIO CPLD testbench, as it had fallen a bit out of date.
Add SGPIO API initialization and control of CPLD decimation feature.
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2013-11-19 19:52:06 -08:00 |
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Jared Boone
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24a8e2bdb5
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Remove CPLD SVF file, as it's not used by anybody (as far as I know).
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2013-11-19 19:45:36 -08:00 |
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Michael Ossmann
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5b14636c2c
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initial firmware support for HackRF One
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2013-11-19 10:01:26 -07:00 |
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Jared Boone
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967e699815
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Another little fix for the two's complement change -- initialize SGPIO data registers to DAC zero values.
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2013-11-17 22:23:08 -08:00 |
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Michael Ossmann
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a909ca641c
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moved GCK1 test point
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2013-11-16 21:39:15 -07:00 |
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Michael Ossmann
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ca2162da29
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forgot to save schematic
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2013-11-16 21:26:07 -07:00 |
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Michael Ossmann
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95ffc704a1
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P28 and P29 reworked, exposed unused SGPIO signals, moved some CPLD JTAG signals to P28
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2013-11-16 21:22:25 -07:00 |
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Jared Boone
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d006ec769c
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Updated CPLD bitstream with two's complement I/O and sample ordering fix.
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2013-11-16 13:41:54 -08:00 |
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Jared Boone
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89eafaa79a
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Remove sample-pair reordering in SGPIO interrupt -- CPLD fixes address this.
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2013-11-16 13:32:41 -08:00 |
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Jared Boone
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7ef9c1e932
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Slow down edges of data lines coming from CPLD.
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2013-11-16 13:31:19 -08:00 |
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Jared Boone
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147f47a3f5
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Invert Q channel data coming from MAX5864, since MAX2837 Q differential pair is reversed.
Do conversion from unsigned to two's-compliment inside FPGA.
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2013-11-16 13:29:00 -08:00 |
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Jared Boone
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9856ea3d14
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Changes due to CGU header API changes.
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2013-11-15 11:41:20 -08:00 |
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Michael Ossmann
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db3ef109fa
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forgot to save schematic when adding clock signals to header
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2013-11-11 20:56:47 -07:00 |
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Michael Ossmann
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06f345239b
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silkscreen tweaks
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2013-11-11 20:49:57 -07:00 |
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Michael Ossmann
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fecc7346b3
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GND test points
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2013-11-11 19:25:28 -07:00 |
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Michael Ossmann
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a8c2c0b6d1
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more decoupling caps
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2013-11-11 19:07:28 -07:00 |
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Michael Ossmann
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26104e6735
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nudged some traces in the RF section
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2013-11-11 18:48:39 -07:00 |
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Michael Ossmann
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c5533b3c96
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reworked zones so LED signals do not cross power planes
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2013-11-11 18:04:45 -07:00 |
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Michael Ossmann
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515b6973aa
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exposed GCK1, GCK2 on expansion P28 instead of extra CPLD pins. also ditched 1V8 on P30
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2013-11-11 17:23:45 -07:00 |
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Michael Ossmann
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f576fc27f0
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rerouted 1V8
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2013-11-11 16:58:30 -07:00 |
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Michael Ossmann
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1b3da372b9
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CPLD JTAG cleanup
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2013-11-11 16:37:43 -07:00 |
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Michael Ossmann
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4577439912
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keep GCK1 on front side
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2013-11-11 16:32:37 -07:00 |
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Michael Ossmann
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174c3b427b
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still cleaning
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2013-11-11 11:09:48 -07:00 |
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Michael Ossmann
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fbcc3b60ec
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still more clean-up
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2013-11-11 10:57:08 -07:00 |
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Michael Ossmann
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923971402c
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a little more clean-up
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2013-11-11 10:51:12 -07:00 |
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Michael Ossmann
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976096f019
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a little clean-up
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2013-11-11 10:25:46 -07:00 |
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Michael Ossmann
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f7e1b15cc9
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more mounting holes
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2013-11-11 10:04:29 -07:00 |
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Michael Ossmann
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20518a77d5
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SPIFI test points
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2013-11-10 23:17:48 -07:00 |
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Michael Ossmann
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5beef42bc5
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track clean-up
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2013-11-10 23:11:04 -07:00 |
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Michael Ossmann
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d6b7202e64
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corner holes
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2013-11-10 20:23:04 -07:00 |
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Michael Ossmann
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198bc7afeb
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TVS diodes for CLKIN and CLKOUT
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2013-11-10 20:19:38 -07:00 |
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Michael Ossmann
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afba176de4
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USB shield break-out
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2013-11-10 20:11:00 -07:00 |
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Michael Ossmann
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1fa9c9aa04
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many test points
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2013-11-10 19:53:25 -07:00 |
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Michael Ossmann
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61176e5371
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selected a new part for USB ESD protection
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2013-11-10 16:49:26 -07:00 |
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Michael Ossmann
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c5ca300a53
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P22 consolidation, expansion
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2013-11-09 23:32:45 -07:00 |
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Michael Ossmann
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d5da6dfee7
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VBUS passives just in case
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2013-11-09 21:17:30 -07:00 |
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Michael Ossmann
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02781f6bc5
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extra footprints for clock signal passives just in case
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2013-11-09 19:45:17 -07:00 |
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Michael Ossmann
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b915582f49
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series resistors on RESET and DFU lines just in case
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2013-11-09 18:52:55 -07:00 |
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Michael Ossmann
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f139288f62
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fixed SMA connector selection
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2013-11-09 18:20:06 -07:00 |
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Michael Ossmann
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297639df6e
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chose a different button
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2013-11-09 17:26:14 -07:00 |
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