4 Commits

Author	SHA1	Message	Date
Jared Boone	5ab31b84e0	Remove FAST attribute from all CPLD I/O, since it changes slew rate by less than 1ns -- not enough to be important at 20MHz or so. Will re-examine later, if we try to push bus speed higher on the final board rev.	2012-07-24 12:48:08 -07:00
Jared Boone	18587e3732	Change all IO on CPLD to LVCMOS33 until we make the move to 1V8 supplies on the MAX5864 and Si5351C.	2012-07-24 12:45:46 -07:00
Jared Boone	d68036f79d	Eliminate ill-conceived HOST_CLK from CPLD. ... Rearrange clocks to not use AC-coupled CLK1 from Si5351C. Move CODEC_CLK to GCLK1, CODEC_X2_CLK (now HOST_CLK, too) to GCLK2. Add trace on Jellybean PCB to connect GCLK2 to LPC4330 pin 56 (P1_12) -- a different SGPIO8.	2012-06-14 19:08:20 -07:00
Jared Boone	07b6f81a6c	Initial implementation of MAX5864 <-> SGPIO interface via Xilinx CoolRunner-II CPLD.	2012-06-09 22:02:45 -07:00