Michael Ossmann
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a751edb11a
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changed to SMT RTC crystal. populating for now. might not in the future.
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2013-11-22 23:40:15 -07:00 |
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Michael Ossmann
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9f94565b03
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resized USB connector holes
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2013-11-22 22:49:10 -07:00 |
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Michael Ossmann
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cd96c356e2
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lengthened USB TVS pads
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2013-11-22 22:35:01 -07:00 |
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Michael Ossmann
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b5dc5a72c1
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nudged USB conector
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2013-11-22 22:02:54 -07:00 |
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Michael Ossmann
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f538386c0b
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nudged pushbuttons
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2013-11-22 21:48:23 -07:00 |
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Michael Ossmann
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b61e05faef
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improved XTAL2 (MAX2837 reference clock) passives
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2013-11-22 18:42:03 -07:00 |
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Michael Ossmann
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72b76a9979
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improved REF_IN passives
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2013-11-22 17:52:28 -07:00 |
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Michael Ossmann
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99803c26cb
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another clock strength adjustment
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2013-11-22 17:50:10 -07:00 |
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Michael Ossmann
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ebaccf46f4
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adjusted clock generator output drive strength
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2013-11-22 17:24:53 -07:00 |
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Michael Ossmann
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575a8394ed
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fixed GP_CLKIN passives
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2013-11-22 17:08:45 -07:00 |
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Michael Ossmann
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15a51cab55
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grounded pushbutton mechanical support
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2013-11-22 09:43:10 -07:00 |
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Michael Ossmann
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04898a7820
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exposed GND through mounting holes
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2013-11-22 09:33:38 -07:00 |
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Michael Ossmann
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42a3582f98
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added resistors to decrease clock signal overshoot
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2013-11-21 18:29:56 -07:00 |
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Michael Ossmann
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0002351b21
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changed some capacitor values to improve low frequency performance
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2013-11-21 18:08:49 -07:00 |
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Jared Boone
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5468a01a9b
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Forgot to include rf_path.h now that its pin setup is called from hackrf_core.
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2013-11-21 10:23:53 -08:00 |
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Jared Boone
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b285b91e4c
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Merge remote-tracking branch 'mossmann/master' into jboone_refactor_20130906
Conflicts:
firmware/common/hackrf_core.h
firmware/common/rffc5071.c
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2013-11-20 18:43:40 -08:00 |
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Jared Boone
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62ab69c3d2
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Giant .gitignore to knock out build files, Xilinx spew, and editor/OS turds.
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2013-11-20 15:51:59 -08:00 |
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Jared Boone
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9db166427f
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Remove I2S pin definitions, since they're too specific for generic/shared HackRF code.
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2013-11-20 15:46:53 -08:00 |
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Jared Boone
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f453e4c377
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Bump libopencm3.
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2013-11-20 15:44:15 -08:00 |
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Jared Boone
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986e4dec93
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Massive rework of Makefile_inc.mk, to support building of heterogeneous (M4+M0) binaries, and easy switching between RAM and SPIFI-bootable builds. Constructive criticism welcome -- I'm sure there's better ways to do this.
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2013-11-20 15:28:28 -08:00 |
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Jared Boone
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02ba23bf68
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Fix broken sgpio-rx project, broken due to massive changes to how RF path and tuning is done.
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2013-11-20 15:24:50 -08:00 |
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Jared Boone
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893c20e41f
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Fix naming problem with SGPIO test project. This is due to my use of VPATH in Makefile_inc.mk, which I'm starting to regret a little bit...
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2013-11-20 15:24:14 -08:00 |
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Jared Boone
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552dbe4a6d
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Add sgpio.c to C files, now required for pin initialization.
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2013-11-20 15:23:26 -08:00 |
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Jared Boone
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6a03f157ff
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With Makefile RAM/SPIFI option, remove/rework redundant "rom_to_ram" projects.
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2013-11-20 15:21:40 -08:00 |
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Jared Boone
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c365d0a37e
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Add memory regions for M0 code to live. In the "rom_to_ram" (SPIFI) version, put M0 binary in ROM. In the RAM version, put M0 code in the destination RAM region.
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2013-11-20 15:14:13 -08:00 |
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Jared Boone
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31a55d0e9b
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Assembly file that includes M0 binary into a .o to be linked into the M4 binary. There's certainly a more elegant way, but for now...
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2013-11-20 15:13:18 -08:00 |
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Jared Boone
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e29ec6b084
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Add default M0 code that just loops forever, if a project doesn't specify any SRC_M0_[CS] files.
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2013-11-20 15:11:54 -08:00 |
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Jared Boone
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91a7ca4983
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Fix return value on SGPIO decimation function.
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2013-11-20 15:08:59 -08:00 |
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Jared Boone
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e3f9e204c1
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Relocate SGPIO pin configuration -- it only needs to be done once.
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2013-11-20 13:22:19 -08:00 |
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Jared Boone
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39276f162c
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Add M0 linker script.
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2013-11-19 19:52:50 -08:00 |
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Jared Boone
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3bf6573dc6
|
Add skip-every-N function to CPLD, where N is controlled by three input pins from the microcontroller.
Updated SGPIO CPLD testbench, as it had fallen a bit out of date.
Add SGPIO API initialization and control of CPLD decimation feature.
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2013-11-19 19:52:06 -08:00 |
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Jared Boone
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24a8e2bdb5
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Remove CPLD SVF file, as it's not used by anybody (as far as I know).
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2013-11-19 19:45:36 -08:00 |
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Michael Ossmann
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5b14636c2c
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initial firmware support for HackRF One
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2013-11-19 10:01:26 -07:00 |
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Jared Boone
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967e699815
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Another little fix for the two's complement change -- initialize SGPIO data registers to DAC zero values.
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2013-11-17 22:23:08 -08:00 |
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Michael Ossmann
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a909ca641c
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moved GCK1 test point
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2013-11-16 21:39:15 -07:00 |
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Michael Ossmann
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ca2162da29
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forgot to save schematic
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2013-11-16 21:26:07 -07:00 |
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Michael Ossmann
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95ffc704a1
|
P28 and P29 reworked, exposed unused SGPIO signals, moved some CPLD JTAG signals to P28
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2013-11-16 21:22:25 -07:00 |
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Jared Boone
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d006ec769c
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Updated CPLD bitstream with two's complement I/O and sample ordering fix.
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2013-11-16 13:41:54 -08:00 |
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Jared Boone
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89eafaa79a
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Remove sample-pair reordering in SGPIO interrupt -- CPLD fixes address this.
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2013-11-16 13:32:41 -08:00 |
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Jared Boone
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7ef9c1e932
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Slow down edges of data lines coming from CPLD.
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2013-11-16 13:31:19 -08:00 |
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Jared Boone
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147f47a3f5
|
Invert Q channel data coming from MAX5864, since MAX2837 Q differential pair is reversed.
Do conversion from unsigned to two's-compliment inside FPGA.
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2013-11-16 13:29:00 -08:00 |
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Jared Boone
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9856ea3d14
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Changes due to CGU header API changes.
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2013-11-15 11:41:20 -08:00 |
|
Michael Ossmann
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db3ef109fa
|
forgot to save schematic when adding clock signals to header
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2013-11-11 20:56:47 -07:00 |
|
Michael Ossmann
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06f345239b
|
silkscreen tweaks
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2013-11-11 20:49:57 -07:00 |
|
Michael Ossmann
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fecc7346b3
|
GND test points
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2013-11-11 19:25:28 -07:00 |
|
Michael Ossmann
|
a8c2c0b6d1
|
more decoupling caps
|
2013-11-11 19:07:28 -07:00 |
|
Michael Ossmann
|
26104e6735
|
nudged some traces in the RF section
|
2013-11-11 18:48:39 -07:00 |
|
Michael Ossmann
|
c5533b3c96
|
reworked zones so LED signals do not cross power planes
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2013-11-11 18:04:45 -07:00 |
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Michael Ossmann
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515b6973aa
|
exposed GCK1, GCK2 on expansion P28 instead of extra CPLD pins. also ditched 1V8 on P30
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2013-11-11 17:23:45 -07:00 |
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Michael Ossmann
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f576fc27f0
|
rerouted 1V8
|
2013-11-11 16:58:30 -07:00 |
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