diff --git a/firmware/cpld/sgpio_if/README.md b/firmware/cpld/sgpio_if/README.md index 44fe9a8c..ee37fb41 100644 --- a/firmware/cpld/sgpio_if/README.md +++ b/firmware/cpld/sgpio_if/README.md @@ -1,6 +1,18 @@ CPLD interface between LPC43xx microcontroller SGPIO peripheral and MAX5864 RF codec. +CPLD-based triggered capture +============================ + +Code related to the paper: + +[M. Bartolucci, J. A. del Peral-Rosado, R. Estatuet-Castillo, J. A. Garcia-Molina, M. Crisci, G. E. Corazza, "Synchronisation of low-cost open source SDRs for navigation applications", Proc. 8th ESA Workshop on Satellite Navigation User Equipment Technologies (NAVITEC), Dec 16 2016](http://spcomnav.uab.es/docs/conferences/Bartolucci_NAVITEC_2016.pdf) + +Please read the paper for hardware correction and additional details. + +* If you don't want to build use `code]default_sync.xsvf` to flash the CPLD +* This is still a very rough implementation. Synchronization can't be disabled! + Requirements ============ diff --git a/firmware/cpld/sgpio_if/default_sync.xsvf b/firmware/cpld/sgpio_if/default_sync.xsvf new file mode 100755 index 00000000..104ab92d Binary files /dev/null and b/firmware/cpld/sgpio_if/default_sync.xsvf differ diff --git a/firmware/cpld/sgpio_if/top.jed b/firmware/cpld/sgpio_if/top.jed index abe1ddf1..36a8d855 100755 --- a/firmware/cpld/sgpio_if/top.jed +++ b/firmware/cpld/sgpio_if/top.jed @@ -1,5 +1,5 @@ Programmer Jedec Bit Map -Date Extracted: Wed Aug 20 08:36:47 2014 +Date Extracted: Fri Jul 8 16:10:08 2016 QF25812* QP100* @@ -375,14 +375,14 @@ L012944 1111111111111111* L012960 1111111010110111* L012976 1111111011010111* L012992 1110101011111111* -L013008 1100111011111111* +L013008 0110111011111111* L013024 1110101011111111* L013040 1111111010110111* L013056 1110101011111111* L013072 1111111010110111* L013088 1111111010110111* L013104 1111111111111111* -L013120 1111111010110111* +L013120 1100111011111111* L013136 1111111011010111* L013152 1111111111111111* L013168 1111111111111111* @@ -395,7 +395,7 @@ L013264 1111111011010111* L013280 1111111011010111* L013296 1111111111111111* L013312 1111111111111111* -L013328 1111111111111111* +L013328 1111111010110111* L013344 1111111111111111* L013360 1111111111111111* L013376 1111111111111111* @@ -410,15 +410,15 @@ L013504 1111111111111111* L013520 1111111111111111* Note Block 2 PLA AND array * -L013536 11110111110111111111111111111111111111111111111111111111111111111011111111111111* -L013616 11011011111001110111111111111111111111111111111111111111111111111011111111111111* -L013696 11110111111011011111111111111111111111111111111111111111111111111111111111111111* -L013776 11111011110111011111111111111111111111111111111111111111111111111111111111111111* +L013536 11110111110111011111111111111111111111111111111111111111111111111011111111111111* +L013616 11011011111001010111111111111111111111111111111111111111111111111011111111111111* +L013696 11110111111011111111111111110111111111111111111111111111111111111111111111111111* +L013776 11111011110111111111111111110111111111111111111111111111111111111111111111111111* L013856 11111111111111111101011111111111111111111111111111111111111111111111111111111111* L013936 11111111111111111110101111111111111111111111111111111111111111111111111111111111* -L014016 11111111111111111111011111110111111111111111111111111111111111111111111111111111* +L014016 11111111111111111111011111111111111111111111111111111101111111111111111111111111* L014096 11111111111011111111111111111111111111111111111111111111111111111111111111111111* -L014176 11111111111111111111101111111011111111111111111111111111111111111111111111111111* +L014176 11111111111111111111101111111111111111111111111111111110111111111111111111111111* L014256 11111111011111111111011111111111111111111111111111111111111111111111111111111111* L014336 11111111101111111111101111111111111111111111111111111111111111111111111111111111* L014416 11111111111111111111011101111111111111111111111111111111111111111111111111111111* @@ -552,8 +552,8 @@ L019376 1111111111111111* L019392 1111111111111111* L019408 1111111111111111* L019424 1111111111111111* -L019440 1111111111111111* -L019456 1111111111111111* +L019440 1111111011100111* +L019456 1111111010110111* L019472 1111111111111111* L019488 1111111111111111* L019504 1111111111111111* @@ -592,8 +592,8 @@ L019984 111111111111111111111111111111111111111111111111111111111111111111111111 L020064 11111111111111111111111111111111111111111111111111111111111111111111111111111111* L020144 11111111111111111111111111111111111111111111111111111111111111111111111111111111* L020224 11111111111111111111111111111111111111111111111111111111111111111111111111111111* -L020304 11111111111111111111111111111111111111111111111111111111111111111111111111111111* -L020384 11111111111111111111111111111111111111111111111111111111111111111111111111111111* +L020304 11111111111111011111111111111111111111111111111111111111111111111111111111111111* +L020384 11111111111101111111111111111111111111111111111111111111111111111111111111111111* L020464 11111111111111111111111111111111111111111111111111111111111111111111111111111111* L020544 11111111111111111111111111111111111111111111111111111111111111111111111111111111* L020624 11111111111111111111111111111111111111111111111111111111111111111111111111111111* @@ -637,7 +637,7 @@ L023584 111111111111111111111111111111111111111111111111111111111111111111111111 L023664 11111111111111111111111111111111111111111111111111111111111111111111111111111111* L023744 11111111111111111111111111111111111111111111111111111111111111111111111111111111* L023824 11111111111111111111111111111111111111111111111111111111111111111111111111111111* -L023904 11111111111111111111111111111111111111111111111111111111111111111111111111111111* +L023904 11111111111110111111111111111111111111111111111111111111111111111111111111111111* L023984 11111111111111111111111111111111111111111111111111111111111111111111111111111111* L024064 11111111111111111111111111111111111111111111111111111111111111111111111111111111* L024144 11111111111111111111111111111111111111111111111111111111111111111111111111111111* @@ -717,8 +717,8 @@ L025576 000001111001111110011111100* L025603 000001111001111110011111100* L025630 000001111001111110011111100* L025657 000001111001111110011111100* -L025684 000001111001111110011111100* -L025711 000001111001111110011111100* +L025684 101101011000010000011111101* +L025711 000001111001111101010000011* L025738 000001111001111110011111100* L025765 000001111001111110011111100* @@ -753,5 +753,5 @@ L025810 0* Note I/O Bank 1 Vcco * L025811 0* -CFB93* -AA7A +CF7BB* +AA74 diff --git a/firmware/cpld/sgpio_if/top.ucf b/firmware/cpld/sgpio_if/top.ucf index db85ab13..aa7ebdf6 100755 --- a/firmware/cpld/sgpio_if/top.ucf +++ b/firmware/cpld/sgpio_if/top.ucf @@ -18,51 +18,57 @@ # the Free Software Foundation, Inc., 51 Franklin Street, # Boston, MA 02110-1301, USA. -NET "CODEC_CLK" LOC="23" |IOSTANDARD=LVCMOS33 | TNM=adc_data; -NET "CODEC_X2_CLK" LOC="27" |IOSTANDARD=LVCMOS33; - NET "CODEC_X2_CLK" TNM_NET = CODEC_X2_CLK; TIMESPEC TS_codec_x2_data = PERIOD "CODEC_X2_CLK" 25 ns; -NET "DA<7>" LOC="35" |IOSTANDARD=LVCMOS33 | TNM=adc_data; -NET "DA<6>" LOC="36" |IOSTANDARD=LVCMOS33 | TNM=adc_data; -NET "DA<5>" LOC="37" |IOSTANDARD=LVCMOS33 | TNM=adc_data; -NET "DA<4>" LOC="39" |IOSTANDARD=LVCMOS33 | TNM=adc_data; -NET "DA<3>" LOC="40" |IOSTANDARD=LVCMOS33 | TNM=adc_data; -NET "DA<2>" LOC="41" |IOSTANDARD=LVCMOS33 | TNM=adc_data; -NET "DA<1>" LOC="42" |IOSTANDARD=LVCMOS33 | TNM=adc_data; -NET "DA<0>" LOC="43" |IOSTANDARD=LVCMOS33 | TNM=adc_data; - -NET "DD<9>" LOC="17" |IOSTANDARD=LVCMOS33 | SLEW=SLOW | TNM=dac_data; -NET "DD<8>" LOC="18" |IOSTANDARD=LVCMOS33 | SLEW=SLOW | TNM=dac_data; -NET "DD<7>" LOC="19" |IOSTANDARD=LVCMOS33 | SLEW=SLOW | TNM=dac_data; -NET "DD<6>" LOC="24" |IOSTANDARD=LVCMOS33 | SLEW=SLOW | TNM=dac_data; -NET "DD<5>" LOC="28" |IOSTANDARD=LVCMOS33 | SLEW=SLOW | TNM=dac_data; -NET "DD<4>" LOC="29" |IOSTANDARD=LVCMOS33 | SLEW=SLOW | TNM=dac_data; -NET "DD<3>" LOC="30" |IOSTANDARD=LVCMOS33 | SLEW=SLOW | TNM=dac_data; -NET "DD<2>" LOC="32" |IOSTANDARD=LVCMOS33 | SLEW=SLOW | TNM=dac_data; -NET "DD<1>" LOC="33" |IOSTANDARD=LVCMOS33 | SLEW=SLOW | TNM=dac_data; -NET "DD<0>" LOC="34" |IOSTANDARD=LVCMOS33 | SLEW=SLOW | TNM=dac_data; - -NET "HOST_DIRECTION" LOC="71" |IOSTANDARD=LVCMOS33 | SLEW=SLOW; -NET "HOST_DISABLE" LOC="76" |IOSTANDARD=LVCMOS33 | SLEW=SLOW; -NET "HOST_CAPTURE" LOC="91" |IOSTANDARD=LVCMOS33 | SLEW=SLOW | TNM=to_host; -NET "HOST_DATA<7>" LOC="77" |IOSTANDARD=LVCMOS33 | SLEW=SLOW | TNM=to_host; -NET "HOST_DATA<6>" LOC="61" |IOSTANDARD=LVCMOS33 | SLEW=SLOW | TNM=to_host; -NET "HOST_DATA<5>" LOC="64" |IOSTANDARD=LVCMOS33 | SLEW=SLOW | TNM=to_host; -NET "HOST_DATA<4>" LOC="67" |IOSTANDARD=LVCMOS33 | SLEW=SLOW | TNM=to_host; -NET "HOST_DATA<3>" LOC="72" |IOSTANDARD=LVCMOS33 | SLEW=SLOW | TNM=to_host; -NET "HOST_DATA<2>" LOC="74" |IOSTANDARD=LVCMOS33 | SLEW=SLOW | TNM=to_host; -NET "HOST_DATA<1>" LOC="79" |IOSTANDARD=LVCMOS33 | SLEW=SLOW | TNM=to_host; -NET "HOST_DATA<0>" LOC="89" |IOSTANDARD=LVCMOS33 | SLEW=SLOW | TNM=to_host; - -NET "HOST_DECIM_SEL<2>" LOC="78" |IOSTANDARD=LVCMOS33; -NET "HOST_DECIM_SEL<1>" LOC="81" |IOSTANDARD=LVCMOS33; -NET "HOST_DECIM_SEL<0>" LOC="90" |IOSTANDARD=LVCMOS33; -NET "HOST_Q_INVERT" LOC="70" |IOSTANDARD=LVCMOS33; - TIMEGRP "adc_data" OFFSET = IN 16 ns BEFORE "CODEC_X2_CLK"; TIMEGRP "dac_data" OFFSET = OUT 15 ns AFTER "CODEC_X2_CLK"; TIMEGRP "to_host" OFFSET = OUT 20 ns AFTER "CODEC_X2_CLK"; +#PACE: Start of Constraints generated by PACE + +#PACE: Start of PACE I/O Pin Assignments +NET "CODEC_CLK" LOC = "P23" | IOSTANDARD = LVCMOS33 ; +NET "CODEC_X2_CLK" LOC = "P27" | IOSTANDARD = LVCMOS33 ; +NET "DA<0>" LOC = "P43" | IOSTANDARD = LVCMOS33 ; +NET "DA<1>" LOC = "P42" | IOSTANDARD = LVCMOS33 ; +NET "DA<2>" LOC = "P41" | IOSTANDARD = LVCMOS33 ; +NET "DA<3>" LOC = "P40" | IOSTANDARD = LVCMOS33 ; +NET "DA<4>" LOC = "P39" | IOSTANDARD = LVCMOS33 ; +NET "DA<5>" LOC = "P37" | IOSTANDARD = LVCMOS33 ; +NET "DA<6>" LOC = "P36" | IOSTANDARD = LVCMOS33 ; +NET "DA<7>" LOC = "P35" | IOSTANDARD = LVCMOS33 ; +NET "DD<0>" LOC = "P34" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ; +NET "DD<1>" LOC = "P33" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ; +NET "DD<2>" LOC = "P32" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ; +NET "DD<3>" LOC = "P30" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ; +NET "DD<4>" LOC = "P29" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ; +NET "DD<5>" LOC = "P28" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ; +NET "DD<6>" LOC = "P24" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ; +NET "DD<7>" LOC = "P19" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ; +NET "DD<8>" LOC = "P18" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ; +NET "DD<9>" LOC = "P17" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ; +NET "HOST_CAPTURE" LOC = "P91" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ; +NET "HOST_DATA<0>" LOC = "P89" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ; +NET "HOST_DATA<1>" LOC = "P79" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ; +NET "HOST_DATA<2>" LOC = "P74" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ; +NET "HOST_DATA<3>" LOC = "P72" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ; +NET "HOST_DATA<4>" LOC = "P67" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ; +NET "HOST_DATA<5>" LOC = "P64" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ; +NET "HOST_DATA<6>" LOC = "P61" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ; +NET "HOST_DATA<7>" LOC = "P77" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ; +NET "HOST_DECIM_SEL<0>" LOC = "P90" | IOSTANDARD = LVCMOS33 ; +NET "HOST_DECIM_SEL<1>" LOC = "P81" | IOSTANDARD = LVCMOS33 ; +NET "HOST_DECIM_SEL<2>" LOC = "P78" | IOSTANDARD = LVCMOS33 ; +NET "HOST_DIRECTION" LOC = "P71" | IOSTANDARD = LVCMOS33 ; +NET "HOST_DISABLE" LOC = "P76" | IOSTANDARD = LVCMOS33 ; +NET "HOST_Q_INVERT" LOC = "P70" | IOSTANDARD = LVCMOS33 ; +NET "HOST_SYNC" LOC = "P55" | IOSTANDARD = LVCMOS33; +NET "HOST_SYNC_CMD" LOC = "P56" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ; + +#PACE: Start of PACE Area Constraints + +#PACE: Start of PACE Prohibit Constraints + +#PACE: End of Constraints generated by PACE diff --git a/firmware/cpld/sgpio_if/top.vhd b/firmware/cpld/sgpio_if/top.vhd index c74bcd0b..a4c11033 100755 --- a/firmware/cpld/sgpio_if/top.vhd +++ b/firmware/cpld/sgpio_if/top.vhd @@ -30,6 +30,8 @@ entity top is Port( HOST_DATA : inout std_logic_vector(7 downto 0); HOST_CAPTURE : out std_logic; + HOST_SYNC_CMD : out std_logic; + HOST_SYNC : in std_logic; HOST_DISABLE : in std_logic; HOST_DIRECTION : in std_logic; HOST_DECIM_SEL : in std_logic_vector(2 downto 0); @@ -56,6 +58,9 @@ architecture Behavioral of top is signal host_data_enable_i : std_logic; signal host_data_capture_o : std_logic; + signal host_sync_o : std_logic := '0'; + signal host_sync_i : std_logic := '0'; + signal host_sync_latched : std_logic := '0'; signal data_from_host_i : std_logic_vector(7 downto 0); signal data_to_host_o : std_logic_vector(7 downto 0); @@ -95,6 +100,9 @@ begin data_from_host_i <= HOST_DATA; HOST_CAPTURE <= host_data_capture_o; + host_sync_i <= HOST_SYNC; + HOST_SYNC_CMD <= host_sync_o; + host_data_enable_i <= not HOST_DISABLE; transfer_direction_i <= to_dac when HOST_DIRECTION = '1' else from_adc; @@ -149,18 +157,30 @@ begin end if; end if; end process; + + process (host_data_enable_i, host_sync_i) + begin + host_sync_o <= host_data_enable_i; + if host_data_enable_i = '1' then + if rising_edge(host_sync_i) then + host_sync_latched <= host_sync_i; + end if; + else + host_sync_latched <= '0'; + end if; + end process; process(host_clk_i) begin if rising_edge(host_clk_i) then if transfer_direction_i = to_dac then if codec_clk_i = '1' then - host_data_capture_o <= host_data_enable_i; + host_data_capture_o <= host_data_enable_i and host_sync_latched; end if; else - if codec_clk_i = '0' then - host_data_capture_o <= host_data_enable_i and decimate_en; - end if; + if codec_clk_i = '0' then + host_data_capture_o <= host_data_enable_i and decimate_en and host_sync_latched; + end if; end if; end if; end process;