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Merge branch 'master' of git://github.com/mossmann/hackrf

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This commit is contained in:
TitanMKD
2012-09-21 18:28:53 +02:00
parent 41fa9388af df740440b0
commit f7dbd7899d
6 changed files with 5058 additions and 4992 deletions
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6
firmware/common/hackrf_core.c
View File

@ -122,14 +122,18 @@ void cpu_clock_init(void)
//FIXME disable I2C
/*
* 12MHz clock is entering LPC XTAL1/OSC input now.
* 12MHz clock is entering LPC XTAL1/OSC input now. On
* Jellybean/Lemondrop, this is a signal from the clock generator. On
* Jawbreaker, there is a 12 MHz crystal at the LPC.
* Set up PLL1 to run from XTAL1 input.
*/
//FIXME a lot of the details here should be in a CGU driver
#ifdef JELLYBEAN
/* configure xtal oscillator for external clock input signal */
CGU_XTAL_OSC_CTRL |= CGU_XTAL_OSC_CTRL_BYPASS;
#endif
/* set xtal oscillator to low frequency mode */
CGU_XTAL_OSC_CTRL &= ~CGU_XTAL_OSC_CTRL_HF;

101
firmware/common/rffc5071.c
View File

@ -24,6 +24,12 @@
* program would do if it had a real spi library
*/
/*
* The actual part on Jawbreaker is the RFFC5072, not the RFFC5071, but the
* RFFC5071 may be installed instead. The only difference between the parts is
* that the RFFC5071 includes a second mixer.
*/
#include <stdint.h>
#include <string.h>
#include "rffc5071.h"
@ -139,24 +145,10 @@ void rffc5071_setup(void)
* not control pins. */
set_RFFC5071_SIPIN(1);
/* Initial settings for Lollipop switches, same for both
* paths. These could use some #defines that iron out the
* (non)inverted signals.
*
* bit0: SWTXB1 (!tx_bypass)
* bit1: SWRXB1 (rx_bypass)
* bit2: SWTXA1 (tx_hp)
* bit3: unused (lock bit)
* bit4: SWRXA1 (rx_hp)
* bit5 SWD1 (!tx_ant)
*
* Unknown whether shift is needed. There are 7 register bits
* to hold 6 GPO bits. */
set_RFFC5071_P1GPO(0b010100<<1);
set_RFFC5071_P2GPO(0b010100<<1);
/* send lock flag on GPO4 */
set_RFFC5071_LOCK(1);
#ifdef JAWBREAKER
/* initial safe switch control settings */
rffc5071_set_gpo(SWITCHCTRL_SAFE);
#endif
/* GPOs are active at all times */
set_RFFC5071_GATE(1);
@ -256,6 +248,15 @@ uint16_t rffc5071_spi_read(uint8_t r) {
serial_delay();
gpio_set(PORT_MIXER_ENX, PIN_MIXER_ENX);
/*
* The device requires a clock while ENX is high after a serial
* transaction. This is not clearly documented.
*/
gpio_set(PORT_MIXER_SCLK, PIN_MIXER_SCLK);
serial_delay();
gpio_clear(PORT_MIXER_SCLK, PIN_MIXER_SCLK);
return data;
#endif /* DEBUG */
}
@ -316,8 +317,17 @@ void rffc5071_spi_write(uint8_t r, uint16_t v) {
gpio_clear(PORT_MIXER_SCLK, PIN_MIXER_SCLK);
}
serial_delay();
gpio_set(PORT_MIXER_ENX, PIN_MIXER_ENX);
/*
* The device requires a clock while ENX is high after a serial
* transaction. This is not clearly documented.
*/
serial_delay();
gpio_set(PORT_MIXER_SCLK, PIN_MIXER_SCLK);
serial_delay();
gpio_clear(PORT_MIXER_SCLK, PIN_MIXER_SCLK);
#endif
}
@ -357,26 +367,58 @@ void rffc5071_regs_commit(void)
}
}
void rffc5071_tx(void) {
void rffc5071_tx(uint8_t gpo) {
LOG("# rffc5071_tx\n");
set_RFFC5071_ENBL(0);
set_RFFC5071_FULLD(0);
set_RFFC5071_MODE(0); /* mixer 1 only (TX) */
set_RFFC5071_MODE(1); /* mixer 2 used for both RX and TX */
#ifdef JAWBREAKER
/* honor SWITCHCTRL_AMP_BYPASS and SWITCHCTRL_HP settings from caller */
gpo &= (SWITCHCTRL_AMP_BYPASS | SWITCHCTRL_HP);
if ((gpo & SWITCHCTRL_AMP_BYPASS) == SWITCHCTRL_AMP_BYPASS)
gpo |= SWITCHCTRL_NO_TX_AMP_PWR;
gpo |= (SWITCHCTRL_TX | SWITCHCTRL_NO_RX_AMP_PWR);
rffc5071_set_gpo(gpo);
#endif
rffc5071_regs_commit();
#ifdef JAWBREAKER
/* honor SWITCHCTRL_MIX_BYPASS setting from caller */
if ((gpo & SWITCHCTRL_MIX_BYPASS) == SWITCHCTRL_MIX_BYPASS)
rffc5071_disable();
else
#endif
rffc5071_enable();
}
void rffc5071_rx(void) {
void rffc5071_rx(uint8_t gpo) {
LOG("# rfc5071_rx\n");
set_RFFC5071_ENBL(0);
set_RFFC5071_FULLD(0);
set_RFFC5071_MODE(1); /* mixer 2 only (RX) */
set_RFFC5071_MODE(1); /* mixer 2 used for both RX and TX */
#ifdef JAWBREAKER
/* honor SWITCHCTRL_AMP_BYPASS and SWITCHCTRL_HP settings from caller */
gpo &= (SWITCHCTRL_AMP_BYPASS | SWITCHCTRL_HP);
if ((gpo & SWITCHCTRL_AMP_BYPASS) == SWITCHCTRL_AMP_BYPASS)
gpo |= SWITCHCTRL_NO_RX_AMP_PWR;
gpo |= SWITCHCTRL_NO_TX_AMP_PWR;
rffc5071_set_gpo(gpo);
#endif
rffc5071_regs_commit();
#ifdef JAWBREAKER
/* honor SWITCHCTRL_MIX_BYPASS setting from caller */
if ((gpo & SWITCHCTRL_MIX_BYPASS) == SWITCHCTRL_MIX_BYPASS)
rffc5071_disable();
else
#endif
rffc5071_enable();
}
/*
* This function turns on both mixer (full-duplex) on the RFFC5071, but our
* current hardware designs do not support full-duplex operation.
*/
void rffc5071_rxtx(void) {
LOG("# rfc5071_rxtx\n");
set_RFFC5071_ENBL(0);
@ -441,14 +483,14 @@ uint16_t rffc5071_config_synth_int(uint16_t lo) {
lo, n_lo, lodiv, fvco, fbkdiv, n, tune_freq);
/* Path 1 */
set_RFFC5071_P1LODIV(lodiv);
set_RFFC5071_P1LODIV(n_lo);
set_RFFC5071_P1N(n);
set_RFFC5071_P1PRESC(fbkdiv >> 1);
set_RFFC5071_P1NMSB(0);
set_RFFC5071_P1NLSB(0);
/* Path 2 */
set_RFFC5071_P2LODIV(lodiv);
set_RFFC5071_P2LODIV(n_lo);
set_RFFC5071_P2N(n);
set_RFFC5071_P2PRESC(fbkdiv >> 1);
set_RFFC5071_P2NMSB(0);
@ -476,6 +518,15 @@ uint16_t rffc5071_set_frequency(uint16_t mhz, uint32_t hz) {
return tune_freq;
}
void rffc5071_set_gpo(uint8_t gpo)
{
/* We set GPO for both paths just in case. */
set_RFFC5071_P1GPO(gpo);
set_RFFC5071_P2GPO(gpo);
rffc5071_regs_commit();
}
#ifdef TEST
int main(int ac, char **av)
{

25
firmware/common/rffc5071.h
View File

@ -31,6 +31,25 @@ extern uint32_t rffc5071_regs_dirty;
#define RFFC5071_REG_SET_CLEAN(r) rffc5071_regs_dirty &= ~(1UL<<r)
#define RFFC5071_REG_SET_DIRTY(r) rffc5071_regs_dirty |= (1UL<<r)
#ifdef JAWBREAKER
/*
* RF switches on Jawbreaker are controlled by General Purpose Outputs (GPO) on
* the RFFC5072.
*/
#define SWITCHCTRL_NO_TX_AMP_PWR (1 << 0) /* turn off TX amp power */
#define SWITCHCTRL_AMP_BYPASS (1 << 1) /* bypass amp section */
#define SWITCHCTRL_TX (1 << 2) /* 1 for TX mode, 0 for RX mode */
#define SWITCHCTRL_MIX_BYPASS (1 << 3) /* bypass RFFC5072 mixer section */
#define SWITCHCTRL_HP (1 << 4) /* 1 for high-pass, 0 for low-pass */
#define SWITCHCTRL_NO_RX_AMP_PWR (1 << 5) /* turn off RX amp power */
/*
* Safe (initial) switch settings turn off both amplifiers and enable both amp
* bypass and mixer bypass.
*/
#define SWITCHCTRL_SAFE (SWITCHCTRL_NO_TX_AMP_PWR | SWITCHCTRL_AMP_BYPASS | SWITCHCTRL_TX | SWITCHCTRL_MIX_BYPASS | SWITCHCTRL_HP | SWITCHCTRL_NO_RX_AMP_PWR)
#endif
/* Initialize chip. Call _setup() externally, as it calls _init(). */
extern void rffc5071_init(void);
extern void rffc5071_setup(void);
@ -56,10 +75,12 @@ extern uint16_t rffc5071_set_frequency(uint16_t mhz, uint32_t hz);
/* Set up rx only, tx only, or full duplex. Chip should be disabled
* before _tx, _rx, or _rxtx are called. */
extern void rffc5071_tx(void);
extern void rffc5071_rx(void);
extern void rffc5071_tx(uint8_t);
extern void rffc5071_rx(uint8_t);
extern void rffc5071_rxtx(void);
extern void rffc5071_enable(void);
extern void rffc5071_disable(void);
extern void rffc5071_set_gpo(uint8_t);
#endif // __RFFC5071_H

27
firmware/sgpio-rx/sgpio-rx.c
View File

@ -311,6 +311,7 @@ void configure_sgpio_test_rx() {
int main(void) {
const uint32_t freq = 2700000000U;
uint8_t switchctrl = 0;
pin_setup();
enable_1v8_power();
@ -326,29 +327,11 @@ int main(void) {
ssp1_set_mode_max2837();
max2837_setup();
rffc5071_setup();
rffc5071_rx();
rffc5071_set_frequency(500, 0); // 500 MHz, 0 Hz (Hz ignored)
#ifdef LOLLIPOP_SWITCH_SET_UP_DONE_IN_RFFC5071
/* lollipop */
uint8_t gpo =
(1 << 0) /* SWTXB1 (!tx_bypass) */
| (0 << 1) /* SWRXB1 (rx_bypass) */
| (1 << 2) /* SWTXA1 (tx_hp) */
| (0 << 3) /* unused */
| (1 << 4) /* SWRXA1 (rx_hp) */
| (0 << 5); /* SWD1 (!tx_ant) */
/* licorice */
//uint8_t gpo =
//(0 << 0) /* MIX_BYPASS */
//| (0 << 1) /* AMP_BYPASS */
//| (0 << 2) /* TX */
//| (0 << 3) /* unused */
//| (0 << 4) /* HP */
//| (0 << 5); /* !AMP_PWR */
rffc5071_reg_write(RFFC5071_GPO, (gpo << 9) | (gpo << 2) | 0x3);
gpio_set(PORT_LED1_3, (PIN_LED1)); /* LED1 on */
#ifdef JAWBREAKER
switchctrl = (SWITCHCTRL_AMP_BYPASS | SWITCHCTRL_HP);
#endif
rffc5071_rx(switchctrl);
rffc5071_set_frequency(500, 0); // 500 MHz, 0 Hz (Hz ignored)
max2837_set_frequency(freq);
max2837_start();

9731
hardware/jawbreaker/jawbreaker.brd
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File diff suppressed because it is too large Load Diff

156
hardware/kicad/hackrf.mod
View File

@ -1,4 +1,4 @@
PCBNEW-LibModule-V1 Wed Sep 12 12:51:27 2012
PCBNEW-LibModule-V1 Thu Sep 20 14:22:18 2012
# encoding utf-8
$INDEX
GSG-0402
@ -8082,69 +8082,6 @@ Po -260 -395
Le 65
$EndPAD
$EndMODULE GSG-SOT363
$MODULE GSG-SKY13350-385LF
Po 0 0 0 15 5032C4C2 00000000 ~~
Li GSG-SKY13350-385LF
Sc 00000000
AR GSG-SKY13350-385LF
Op 0 0 0
T0 0 0 197 118 0 30 N V 21 N "GSG-SKY13350-385LF"
T1 0 0 197 118 0 30 N I 21 N "VAL**"
DC -236 -236 -197 -197 70 21
DS 197 197 -197 197 70 21
DS -197 197 -197 -197 70 21
DS -197 -197 197 -197 70 21
DS 197 -197 197 197 70 21
$PAD
Sh "1" R 169 60 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po -211 -98
Le 41110432
$EndPAD
$PAD
Sh "3" R 79 240 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po 0 177
Le 41110432
$EndPAD
$PAD
Sh "4" R 169 60 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po 211 98
Le 20
$EndPAD
$PAD
Sh "5" R 169 60 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po 211 -98
Le 4149
$EndPAD
$PAD
Sh "6" R 79 240 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po 0 -177
Le 41110432
.SolderPasteRatio -0.04
$EndPAD
$PAD
Sh "2" R 169 60 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po -211 98
Le 839724792
$EndPAD
$EndMODULE GSG-SKY13350-385LF
$MODULE GSG-SKY13317-373LF
Po 0 0 0 15 5032C63B 00000000 ~~
Li GSG-SKY13317-373LF
@ -8539,8 +8476,25 @@ Ne 0 ""
Po 0 0
$EndPAD
$EndMODULE GSG-0402-SHORT-20MIL
$MODULE GSG-HOLE126MIL
Po 0 0 0 15 5050D97F 00000000 ~~
Li GSG-HOLE126MIL
Sc 00000000
AR GSG-HOLE260MIL
Op 0 0 0
T0 0 0 394 394 0 80 N V 21 N "HOLE126MIL"
T1 0 0 394 394 0 80 N V 21 N "VAL**"
$PAD
Sh "" C 1260 1260 0 0 0
Dr 1260 0 0
At STD N 00C0FFFF
Ne 0 ""
Po 0 0
Le 235021312
$EndPAD
$EndMODULE GSG-HOLE126MIL
$MODULE GSG-HEADER-1x2-SHORTED
Po 0 0 0 15 5048D16E 00000000 ~~
Po 0 0 0 15 505B6DA1 00000000 ~~
Li GSG-HEADER-1x2-SHORTED
Kw CONN
Sc 00000000
@ -8575,26 +8529,72 @@ $EndPAD
$PAD
Sh "" R 600 100 0 0 0
Dr 0 0 0
At SMD N 00888000
At SMD N 00808000
Ne 0 ""
Po 0 0
$EndPAD
$EndMODULE GSG-HEADER-1x2-SHORTED
$MODULE GSG-HOLE126MIL
Po 0 0 0 15 5050D97F 00000000 ~~
Li GSG-HOLE126MIL
$MODULE GSG-SKY13350-385LF
Po 0 0 0 15 5032C4C2 00000000 ~~
Li GSG-SKY13350-385LF
Sc 00000000
AR GSG-HOLE260MIL
AR GSG-SKY13350-385LF
Op 0 0 0
T0 0 0 394 394 0 80 N V 21 N "HOLE126MIL"
T1 0 0 394 394 0 80 N V 21 N "VAL**"
.SolderPasteRatio -0.02
T0 0 0 197 118 0 30 N V 21 N "GSG-SKY13350-385LF"
T1 0 0 197 118 0 30 N I 21 N "VAL**"
DC -236 -236 -197 -197 70 21
DS 197 197 -197 197 70 21
DS -197 197 -197 -197 70 21
DS -197 -197 197 -197 70 21
DS 197 -197 197 197 70 21
$PAD
Sh "" C 1260 1260 0 0 0
Dr 1260 0 0
At STD N 00C0FFFF
Sh "1" R 169 60 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po 0 0
Le 235021312
Po -211 -98
Le 41110432
$EndPAD
$EndMODULE GSG-HOLE126MIL
$PAD
Sh "3" R 79 240 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po 0 177
Le 41110432
$EndPAD
$PAD
Sh "4" R 169 60 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po 211 98
Le 20
$EndPAD
$PAD
Sh "5" R 169 60 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po 211 -98
Le 4149
$EndPAD
$PAD
Sh "6" R 79 240 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po 0 -177
Le 41110432
$EndPAD
$PAD
Sh "2" R 169 60 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po -211 98
Le 839724792
$EndPAD
$EndMODULE GSG-SKY13350-385LF
$EndLIBRARY