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CPLD tool: Add checksum and code generation mode flags.

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This commit is contained in:
Jared Boone
2019-02-22 13:35:47 -08:00
parent 5695f29c8d
commit f70186644c
1 changed files with 18 additions and 14 deletions
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4
firmware/tools/cpld_crc.py
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@ -7,6 +7,9 @@
import argparse import argparse
parser = argparse.ArgumentParser() parser = argparse.ArgumentParser()
action_group = parser.add_mutually_exclusive_group(required=True)
action_group.add_argument('--checksum', action='store_true', help='Calculate bitstream read-back CRC32 value')
action_group.add_argument('--code', action='store_true', help='Generate C code for bitstream loading/programming/verification')
parser.add_argument('--crcmod', action='store_true', help='Use Python crcmod library instead of built-in CRC32 code') parser.add_argument('--crcmod', action='store_true', help='Use Python crcmod library instead of built-in CRC32 code')
parser.add_argument('--debug', action='store_true', help='Enable debug output') parser.add_argument('--debug', action='store_true', help='Enable debug output')
parser.add_argument('hackrf_xc2c_cpld_xsvf', type=str, help='HackRF Xilinx XC2C64A CPLD XSVF file containing erase/program/verify phases') parser.add_argument('hackrf_xc2c_cpld_xsvf', type=str, help='HackRF Xilinx XC2C64A CPLD XSVF file containing erase/program/verify phases')
@ -75,6 +78,7 @@ assert(address_sequence == expected_address_sequence)
data = data[1] data = data[1]
byte_count = (274 + 7) // 8 byte_count = (274 + 7) // 8
if args.checksum:
if args.crcmod: if args.crcmod:
# Use a proper CRC library # Use a proper CRC library
import crcmod import crcmod