h1r9: MAX2839 driver updates
This commit is contained in:
Michael Ossmann
committed by
Mike Walters
Mike Walters
parent
a72f084ff0
commit
f4817b60a3
@ -36,17 +36,17 @@
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/* Default register values. */
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static const uint16_t max2839_regs_default[MAX2839_NUM_REGS] = {
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0x000, /* 0 */
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0x00C, /* 1 */
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0x00c, /* 1: data sheet says 0x00c but read 0x22c */
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0x080, /* 2 */
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0x1b9, /* 3 */
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0x1b9, /* 3: data sheet says 0x1b9 but read 0x1b0 */
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0x3e6, /* 4 */
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0x100, /* 5 */
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0x000, /* 6 */
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0x208, /* 7 */
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0x220, /* 8 */
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0x220, /* 8: data sheet says 0x220 but read 0x000 */
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0x018, /* 9 */
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0x00c, /* 10 */
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0x004, /* 11 */
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0x004, /* 11: data sheet says 0x004 but read 0x000 */
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0x24f, /* 12 */
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0x150, /* 13 */
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0x3c5, /* 14 */
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@ -56,17 +56,24 @@ static const uint16_t max2839_regs_default[MAX2839_NUM_REGS] = {
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0x155, /* 18 */
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0x153, /* 19 */
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0x249, /* 20 */
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0x02d, /* 21 */
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0x02d, /* 21: data sheet says 0x02d but read 0x13d */
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0x1a9, /* 22 */
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0x24f, /* 23 */
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0x180, /* 24 */
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0x000, /* 25 */
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0x000, /* 25: data sheet says 0x000 but read 0x00a */
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0x3c0, /* 26 */
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0x200, /* 27 */
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0x200, /* 27: data sheet says 0x200 but read 0x22a */
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0x0c0, /* 28 */
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0x03f, /* 29 */
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0x380, /* 30 */
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0x340}; /* 31 */
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0x03f, /* 29: data sheet says 0x03f but read 0x07f */
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0x300, /* 30: data sheet says 0x300 but read 0x398 */
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0x340}; /* 31: data sheet says 0x340 but read 0x359 */
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/*
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* All of the discrepancies listed above are in fields that either don't matter
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* or are undocumented except "set to recommended value". We set them to the
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* data sheet defaults even though the inital part we tested started up with
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* different settings.
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*/
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/* Set up all registers according to defaults specified in docs. */
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static void max2839_init(max2839_driver_t* const drv)
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@ -88,7 +95,27 @@ static void max2839_init(max2839_driver_t* const drv)
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void max2839_setup(max2839_driver_t* const drv)
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{
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max2839_init(drv);
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// TODO
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/* Use SPI control instead of B0-B7 pins for gain settings. */
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set_MAX2839_LNAgain_SPI(drv, 1);
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set_MAX2839_VGAgain_SPI(drv, 1);
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set_MAX2839_TX_VGA_Gain_SPI(drv, 1);
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/* enable RXINB */
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set_MAX2839_MIMO_SELECT(drv, 1);
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/* set gains for unused RXINA path to minimum */
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set_MAX2839_LNA1gain(drv, MAX2839_LNA1gain_M32);
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set_MAX2839_Rx1_VGAgain(drv, 0x3f);
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//set_MAX2839_TX_VGA_GAIN(drv, 0x18);
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/* maximum RX output common-mode voltage */
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set_MAX2839_RX_VCM(drv, MAX2839_RX_VCM_1_35);
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//FIXME do something with HPFSM/HPC?
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//FIXME do something with LPF?
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max2839_regs_commit(drv);
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}
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@ -107,9 +134,10 @@ static void max2839_write(max2839_driver_t* const drv, uint8_t r, uint16_t v)
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uint16_t max2839_reg_read(max2839_driver_t* const drv, uint8_t r)
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{
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if ((drv->regs_dirty >> r) & 0x1) {
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// always read actual value from SPI for now
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//if ((drv->regs_dirty >> r) & 0x1) {
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drv->regs[r] = max2839_read(drv, r);
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};
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//};
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return drv->regs[r];
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}
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@ -154,14 +182,16 @@ void max2839_start(max2839_driver_t* const drv)
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void max2839_tx(max2839_driver_t* const drv)
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{
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set_MAX2839_LPFblock_MODE(drv, MAX2839_ModeCtrl_TxLPF);
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// FIXME does this do anything without LPFmode_SPI set?
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// do we need it to?
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set_MAX2839_LPFmode(drv, MAX2839_LPFmode_TxLPF);
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max2839_regs_commit(drv);
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max2839_set_mode(drv, MAX2839_MODE_TX);
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}
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void max2839_rx(max2839_driver_t* const drv)
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{
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set_MAX2839_LPFblock_MODE(drv, MAX2839_ModeCtrl_RxLPF);
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set_MAX2839_LPFmode(drv, MAX2839_LPFmode_RxLPF);
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max2839_regs_commit(drv);
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max2839_set_mode(drv, MAX2839_MODE_RX);
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}
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@ -276,24 +306,24 @@ bool max2839_set_lna_gain(max2839_driver_t* const drv, const uint32_t gain_db) {
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uint16_t val;
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switch(gain_db){
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case 40:
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val = MAX2839_LNA1gain_MAX;
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val = MAX2839_LNA2gain_MAX;
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break;
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case 32:
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val = MAX2839_LNA1gain_M8;
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val = MAX2839_LNA2gain_M8;
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break;
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case 24:
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val = MAX2839_LNA1gain_M16;
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// FIXME correct missing settings with VGA adjustment?
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case 16:
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val = MAX2839_LNA2gain_M16;
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break;
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case 8:
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val = MAX2839_LNA1gain_M32;
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break;
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case 0:
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val = MAX2839_LNA1gain_M32;
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val = MAX2839_LNA2gain_M32;
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break;
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default:
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return false;
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}
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set_MAX2839_LNA1gain(drv, val);
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set_MAX2839_LNA2gain(drv, val);
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max2839_reg_commit(drv, 5);
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return true;
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}
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@ -303,7 +333,7 @@ bool max2839_set_vga_gain(max2839_driver_t* const drv, const uint32_t gain_db) {
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return false;
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}
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set_MAX2839_Rx1_VGAgain(drv, (63-gain_db));
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set_MAX2839_Rx2_VGAgain(drv, (63-gain_db));
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max2839_reg_commit(drv, 5);
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return true;
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}
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@ -37,10 +37,9 @@ __MREG__(MAX2839_LNAband,1,1,2)
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__MREG__(MAX2839_RESERVED_1_2,1,2,1)
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__MREG__(MAX2839_MIMO_SELECT,1,3,1)
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__MREG__(MAX2839_iqerr_trim,1,9,6)
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// TODO: D9:D4 but shows only 5 bits for values?
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// 0b00000 = +4.0 degree phase error
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// 0b01111 = 0.0
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// 0b11111 = -4.0
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// 0b000000 = +4.0 degree phase error
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// 0b011111 = 0.0
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// 0b111111 = -4.0
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/* REG 2 */
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__MREG__(MAX2839_LNAgain_SPI,2,0,1)
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@ -80,16 +79,24 @@ __MREG__(MAX2839_LNA1gain,5,1,2)
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#define MAX2839_LNA1gain_M16 0b010
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#define MAX2839_LNA1gain_M32 0b011
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__MREG__(MAX2839_Rx1_VGAgain,5,7,6)
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__MREG__(MAX2839_LPFblock_MODE,5,9,2)
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#define MAX2839_ModeCtrl_RxCalibration 0
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#define MAX2839_ModeCtrl_RxLPF 1
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#define MAX2839_ModeCtrl_TxLPF 2
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#define MAX2839_ModeCtrl_LPFTrim 3
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__MREG__(MAX2839_LPFmode,5,9,2)
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#define MAX2839_LPFmode_RxCalibration 0
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#define MAX2839_LPFmode_RxLPF 1
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#define MAX2839_LPFmode_TxLPF 2
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#define MAX2839_LPFmode_LPFTrim 3
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/* REG 6 */
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__MREG__(MAX2839_LNA2gain_SPI,6,1,2)
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__MREG__(MAX2839_LNA2gain,6,1,2)
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#define MAX2839_LNA2gain_MAX 0b000 // Pad in 8dB steps, bits reversed
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#define MAX2839_LNA2gain_M8 0b001
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#define MAX2839_LNA2gain_M16 0b010
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#define MAX2839_LNA2gain_M32 0b011
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__MREG__(MAX2839_Rx2_VGAgain,6,7,6)
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__MREG__(MAX2839_RX_VGAoutput,6,9,2)
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__MREG__(MAX2839_RX_VCM,6,9,2)
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#define MAX2839_RX_VCM_1_0 0b00 // 1.0 V
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#define MAX2839_RX_VCM_1_1 0b01 // 1.1 V
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#define MAX2839_RX_VCM_1_2 0b10 // 1.2 V
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#define MAX2839_RX_VCM_1_35 0b11 // 1.35 V
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/* REG 7 */
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__MREG__(MAX2839_RESERVED_7_0,7,0,1)
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@ -103,7 +110,7 @@ __MREG__(MAX2839_RSSIinput,7,9,1)
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/* REG 8 */
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__MREG__(MAX2839_RESERVED_8_0,8,0,1)
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__MREG__(MAX2839_VGAgain_SPI,8,1,1)
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__MREG__(MAX2839_LPFmode,8,2,1)
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__MREG__(MAX2839_LPFmode_SPI,8,2,1)
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__MREG__(MAX2839_RESERVED_8_9,8,9,7)
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/* REG 9 */
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@ -214,7 +221,7 @@ __MREG__(MAX2839_VAS_Test_Signal_Select,26,9,4)
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/* REG 27 */
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__MREG__(MAX2839_TX_LO_IQ_Phase_SPI_Adjust_Addr27,27,5,6)
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__MREG__(MAX2839_TX_LO_IQ_Phase_SPI_Adjust_Enable,27,6,1)
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__MREG__(MAX2839_TX_VGA_Gain_SPI_Ctrl_Enable,27,7,1)
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__MREG__(MAX2839_TX_VGA_Gain_SPI,27,7,1)
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__MREG__(MAX2839_TX_DC_Offset_SPI_Adjust_Enable,27,8,1)
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__MREG__(MAX2839_RESERVED_27_9,27,9,1)
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